HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 715

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

(Example 1-2)
• Register specifications
(Example 1-3)
• Register specifications
BARA = H'00037226, BAMRA = H'00000000, BBRA = H'0056, BARB = H'0003722E,
BAMRB = H'00000000, BBRB = H'0056, BDRB = H'00000000, BDMRB = H'00000000,
BRCR = H'00000008
Specified conditions: Channel A/channel B sequential mode
 Channel A
 Channel B
BARA = H'00027128, BAMRA = H'00000000, BBRA = H'005A, BARB = H'00031415,
BAMRB = H'00000000, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000,
BRCR = H'00300000
Specified conditions: Channel A/channel B independent mode
 Channel A
 Channel B
A user break occurs after an instruction of address H'00000404 is executed or before
instructions of addresses H'00008010 to H'00008016 are executed.
Address: H'00037226, Address mask: H'00000000
Bus cycle: L bus/instruction fetch (before instruction execution)/read/word
Address: H'0003722E, Address mask: H'00000000
Data:
Bus cycle: L bus/instruction fetch (before instruction execution)/read/word
After an instruction with address H'00037226 is executed, a user break occurs before an
instruction with address H'0003722E is executed.
Address: H'00027128, Address mask: H'00000000
Bus cycle: L bus/instruction fetch (before instruction execution)/write/word
Address: H'00031415, Address mask: H'00000000
Data:
Bus cycle:
On channel A, no user break occurs since instruction fetch is not a write cycle. On channel
B, no user break occurs since instruction fetch is performed for an even address.
H'00000000, Data mask: H'00000000
H'00000000, Data mask: H'00000000
L bus/instruction fetch (before instruction execution)/read (operand size is
not included in the condition)
Rev. 1.00, 02/04, page 677 of 804