HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 85

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

2.5
2.5.1
Instruction Length: All instructions have a fixed length of 16 bits and are executed in the
sequential pipeline. In the sequential pipeline, almost all instructions can be executed in one
cycle. All data are handled in longwords (32 bits). Memory can be accessed in bytes, words, or
longwords. In this case, byte or word data is sign-extended and handled as longword data.
Immediate data is sign-extended to longword size for arithmetic operations (MOV, ADD, and
CMP/EQ instructions) or zero-extended to longword size for logical operations (TST, AND, OR,
and XOR instructions).
Load/Store Architecture: Basic operations are executed between registers. In operations
involving memory, data is first loaded into a register (load/store architecture). However, bit
manipulation instructions such as AND are executed directly on memory.
Delayed Branching: Unconditional branch instructions are executed as delayed branches. With a
delayed branch instruction, the branch is made after execution of the instruction immediately
following the delayed branch instruction. This minimizes disruption of the pipeline when a branch
is made. An example is shown below. This LSI supports two types of conditional branch
instructions: delayed branch instruction and normal branch instruction.
T Bit: The result of a comparison is indicated by the T bit in the status register (SR), and a
conditional branch is performed according to whether the result is True or False. Processing speed
has been improved by keeping the number of instructions that modify the T bit to a minimum. An
example of using the T bit is shown below.
ADD
set
Features of Instructions
Instruction Execution Method
BRA
ADD
ADD
CMP/EQ
BT
TRGET
R1, R0
#1, R0
#0, R0
TRGET
branching to the TRGET.
to 1 (R0 = 0).
; ADD instruction is executed before
; The T bit cannot be modified by the
instruction.
; The T bit is set to 1 if R0 is 0.
; Branch to the TRGET if the T bit is
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