HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 27

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Figure 16.6 Transmit Data Stop Function Flowchart ................................................................. 470
Figure 16.7 Sample Serial Reception Flowchart (1)................................................................... 471
Figure 16.8 Sample Serial Reception Flowchart (2)................................................................... 472
Figure 16.9 Example of SCIF Receive Operation
Figure 16.10 CTS Control Operation ......................................................................................... 474
Figure 16.11 RTS Control Operation ......................................................................................... 475
Figure 16.12 Data Format in Clock Synchronous Communication ............................................ 476
Figure 16.13 Sample SCIF Initialization Flowchart (1) (Transmission) .................................... 477
Figure 16.13 Sample SCIF Initialization Flowchart (2) (Reception).......................................... 478
Figure 16.13 Sample SCIF Initialization Flowchart (3)
Figure 16.14 Sample Serial Transmission Flowchart (1)
Figure 16.14 Sample Serial Transmission Flowchart (2)
Figure 16.15 Sample Serial Reception Flowchart (1)
Figure 16.15 Sample Serial Reception Flowchart (2)
Figure 16.16 Sample Simultaneous Serial Transmission and Reception Flowchart (1)
Figure 16.16 Sample Simultaneous Serial Transmission and Reception Flowchart (2)
Figure 16.17 Receive Data Sampling Timing in Asynchronous Mode ...................................... 488
Section 17 Boot Function (BOOT)
Figure 17.1 Block Diagram of Boot Function ............................................................................ 492
Figure 17.2 External Memory Space in Boot Mode ................................................................... 494
Figure 17.3 Procedure for Execution of Boot Processing........................................................... 497
Section 18 USB Pin Multiplex Controller (USBPM)
Figure 18.1 Block Diagram of this USB..................................................................................... 500
Figure 18.2 Example 1 of Connection between USB Function Controller
Figure 18.3 Example 2 of Connection between USB Function Controller
Figure 18.4 Example of Connection USB Host Controller and External Circuit ....................... 507
Section 20 USB Function Controller (USBF)
Figure 20.1 Block Diagram of USB Function Controller ........................................................... 549
Figure 20.2 Example of Endpoint Configuration (1) .................................................................. 582
Figure 20.3 Example of Endpoint Configuration (2) .................................................................. 585
Figure 20.4 Cable Connection Operation ................................................................................... 586
and External Circuit................................................................................................. 505
and External Circuit................................................................................................. 506
(Example with 8-Bit Data, Parity, One Stop Bit) .................................................... 474
(Simultaneous Transmission and Reception) ........................................................ 479
(First Transmission after Initialization) ................................................................. 480
(Second and Subsequent Transmission) ................................................................ 480
(First Reception after Initialization) ...................................................................... 481
(Second and Subsequent Reception) ..................................................................... 482
(First Transfer after Initialization)......................................................................... 483
(Second and Subsequent Transfer) ........................................................................ 484
Rev. 1.00, 02/04, page xxvii of xxxviii