OM13008,598 NXP Semiconductors, OM13008,598 Datasheet
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UM10441 LPC1224/25/26/27 User manual Rev. 1.1 — 10 March 2011 Document information Info Content Keywords LPC122x, LPC1227, LPC1226, LPC1225, LPC1224, ARM Cortex-M0, microcontroller Abstract LPC122x User manual User manual ...
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... NXP Semiconductors Revision history Rev Date Description 1.01 <tbd> LPC122x User manual • Pinout updated for pins RTCXOUT and RTCXIN (LQFP64 package) in • DRV bit updated for IOCON registers selected Low mode current selected. 1 20110215 LPC122x User manual Contact information For more information, please visit: http://www ...
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UM10441 Chapter 1: LPC122x Introductory information Rev. 1.1 — 10 March 2011 1.1 Introduction The LPC122x extend NXP's 32-bit ARM microcontroller continuum and target a wide range of industrial applications in the areas of factory and home automation. Benefitting from ...
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... NXP Semiconductors – PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the system oscillator or the internal RC oscillator. – Clock output function with divider that can reflect the system oscillator clock, IRC clock, main clock, and Watchdog clock. – ...
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... NXP Semiconductors 1.3 Ordering information Table 1. Ordering information Type number Package Name Description LPC1227FBD64/301 LQFP64 LQFP64: plastic low profile quad flat package; 64 leads; body 1.4 mm SOT314-2 LPC1226FBD64/301 LQFP64 LQFP64: plastic low profile quad flat package; 64 leads; body 1.4 mm SOT314-2 LPC1225FBD64/321 LQFP64 LQFP64: plastic low profile quad flat package; 64 leads; body 1.4 mm SOT314-2 LPC1225FBD64/301 LQFP64 LQFP64: plastic low profile quad flat package ...
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... NXP Semiconductors 1.4 Block diagram LPC122x GPIO ports HIGH-SPEED PIO0/1/2 GPIO SCK SSEL SSP/SPI MISO MOSI RXD0 UART0 RS-485 TXD0 DTR0, DSR0, CTS0, DCD0, RI0, RTS0 RXD1 UART1 TXD1 SCL 2 I C-bus SDA 4 × MAT 32-bit COUNTER/TIMER 0/1 4 × CAP 2 × MAT 16-bit COUNTER/TIMER 0/1 2 × ...
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UM10441 Chapter 2: LPC122x Memory map Rev. 1.1 — 10 March 2011 2.1 How to read this chapter Table 3 shows the memory configuration for the LPC122x parts. Table 3. LPC122x memory configuration Type number LPC1227FBD64/301 LPC1227FBD48/301 LPC1226FBD64/301 LPC1226FBD48/301 LPC1225FBD64/321 ...
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... NXP Semiconductors 2.3 Memory allocation LPC122x 4 GB reserved private peripheral bus reserved AHB peripherals reserved APB peripherals 1 GB reserved 8 kB boot ROM reserved 8 kB custom ROM reserved 16 kB NXP library ROM reserved 8 kB SRAM (LPC1225/6/ SRAM (LPC1224) reserved 128 kB on-chip flash (LPC1227/301) ...
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UM10441 Chapter 3: LPC122x Nested Vectored Interrupt Controller (NVIC) Rev. 1.1 — 10 March 2011 3.1 How to read this chapter The NVIC is part of the ARM Cortex-M0 system block is identical on all LPC122x parts. 3.2 Features • ...
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... NXP Semiconductors Table 4. Connection of interrupt sources to the Vectored Interrupt Controller Exception Number UM10441 User manual Chapter 3: LPC122x Nested Vectored Interrupt Controller (NVIC) Function Flag(s) CT16B1 Match Capture CT32B0 Match Capture CT32B1 Match Capture SSP Tx FIFO half empty Rx FIFO half full Rx Timeout ...
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UM10441 Chapter 4: LPC122x System control (SYSCON) Rev. 1.1 — 10 March 2011 4.1 How to read this chapter The system control block is identical on all LPC122x parts. 4.2 Introduction The system configuration block controls oscillators, start logic, and ...
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... NXP Semiconductors SYSCONFIG irc_osc_clk wdt_osc_clk MAINCLKSEL sys_pllclkout irc_osc_clk SYS PLL sys_osc_clk sys_pllclkin SYSPLLCLKSEL irc_osc_clk wdt_osc_clk rtc_osc 1 Hz clk rtc_osc 1 Hz delayed clk rtc_osc 1 kHz clk syscon RTC clock divider Fig 3. LPC122x CGU block diagram 4.5 Register description All registers, regardless of size, are on word address boundaries. Details of the registers appear in the description of each function ...
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... NXP Semiconductors Table 6. Register overview: system control block (base address 0x4004 8000) Name SYSMEMREMAP PRESETCTRL SYSPLLCTRL SYSPLLSTAT - SYSOSCCTRL WDTOSCCTRL IRCCTRL - SYSRESSTAT - SYSPLLCLKSEL SYSPLLCLKUEN - MAINCLKSEL MAINCLKUEN SYSAHBCLKDIV - SYSAHBCLKCTRL - - SSPCLKDIV UART0CLKDIV UART1CLKDIV RTCCLKDIV - CLKOUTCLKSEL CLKOUTUEN CLKOUTDIV - PIOPORCAP0 PIOPORCAP1 UM10441 User manual Chapter 4: LPC122x System control (SYSCON) ...
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... NXP Semiconductors Table 6. Register overview: system control block (base address 0x4004 8000) Name - IOCONFIGCLKDIV6 R/W IOCONFIGCLKDIV5 R/W IOCONFIGCLKDIV4 R/W IOCONFIGCLKDIV3 R/W IOCONFIGCLKDIV2 R/W IOCONFIGCLKDIV1 R/W IOCONFIGCLKDIV0 R/W BODCTRL SYSTCKCAL AHBPRIO - IRQLATENCY INTNMI - STARTAPRP0 STARTERP0 STARTRSRP0CLR STARTSRP0 STARTAPRP1 STARTERP1 STARTRSRP1CLR STARTSRP1 - PDSLEEPCFG ...
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... NXP Semiconductors Table 6. Register overview: system control block (base address 0x4004 8000) Name PDAWAKECFG PDRUNCFG - DEVICE_ID Remark: The flash configuration block resides in its own memory area but is listed together with the system control registers. Table 7. Register overview: flash configuration (base address 0x5006 0000) ...
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... NXP Semiconductors 4.5.2 Peripheral reset control register This register allows software to reset individual peripherals bit in this register is set to 0, the corresponding peripheral is reset. Writing a 1 de-asserts the reset. Bit 15 of this register overwrites the flash timing for read access. Table 9. Peripheral reset control register (PRESETCTRL, address 0x4004 8004) bit ...
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... NXP Semiconductors Table 9. Peripheral reset control register (PRESETCTRL, address 0x4004 8004) bit description Bit Symbol 15 FLASH_OVERRIDE 31:16 - 4.5.3 System PLL control register This register connects and enables the system PLL and configures the PLL multiplier and divider values. The PLL accepts an input frequency from 10 MHz to 25 MHz from various clock sources ...
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... NXP Semiconductors 4.5.5 System oscillator control register This register configures the frequency range for the system oscillator. Table 12. System oscillator control register (SYSOSCCTRL, address 0x4004 8020) bit description Bit Symbol 0 BYPASS 1 FREQRANGE 31:2 - 4.5.6 Watchdog oscillator control register This register configures the watchdog oscillator. The oscillator consists of an analog and a digital part ...
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... NXP Semiconductors Table 13. Watchdog oscillator control register (WDTOSCCTRL, address 0x4004 8024) bit description Bit Symbol 8:5 FREQSEL 31:9 - 4.5.7 Internal resonant crystal control register This register is used to trim the on-chip 12 MHz oscillator. The trim value is factory-preset and written by the boot code on start-up. ...
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... NXP Semiconductors Table 15. System reset status register (SYSRESSTAT, address 0x4004 8030) bit description Bit Symbol 1 EXTRST 2 WDT 3 BOD 4 SYSRST 31:5 - 4.5.9 System PLL clock source select register This register selects the clock source for the system PLL. The SYSPLLCLKUEN register (see ...
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... NXP Semiconductors Table 17. System PLL clock source update enable register (SYSPLLCLKUEN, address 0x4004 8044) bit description Bit Symbol 0 ENA 31:1 - 4.5.11 Main clock source select register This register selects the main system clock which can be either any input to the system PLL, the output from the system PLL (sys_pllclkout), or the watchdog or IRC oscillators directly ...
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... NXP Semiconductors Table 20. System AHB clock divider register (SYSAHBCLKDIV, address 0x4004 8078) bit description Bit Symbol 7:0 DIV 31:8 - 4.5.14 System AHB clock control register The AHBCLKCTRL register enables the clocks to individual system and peripheral blocks. The system clock (sys_ahb_clk[0], bit 0 in the AHBCLKCTRL register) provides the clock for the AHB to APB bridge, the AHB matrix, the ARM Cortex-M0, the SYSCON block, and the PMU ...
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... NXP Semiconductors Table 21. System AHB clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit description Bit Symbol 7 CT16B0 8 CT16B1 9 CT32B0 10 CT32B1 11 SSP 12 UART0 13 UART1 14 ADC 15 WDT 16 IOCON 17 DMA 18 - UM10441 User manual Chapter 4: LPC122x System control (SYSCON) …continued Value Description Enables clock for 16-bit counter/timer 0. ...
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... NXP Semiconductors Table 21. System AHB clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit description Bit Symbol 19 RTC 20 CMP 27: GPIO2 30 GPIO1 31 GPIO0 4.5.15 SSP clock divider register This register configures the SSP peripheral clock SSP_PCLK. The SSP_PCLK can be shut down by setting the DIV bits to 0x0. ...
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... NXP Semiconductors Table 23. UART0 clock divider register (UART0CLKDIV, address 0x4004 8098) bit description Bit Symbol 7:0 DIV 31:8 - 4.5.17 UART1 clock divider register This register configures the UART1 peripheral clock UART1_PCLK. The UART1_PCLK can be shut down by setting the DIV bits to 0x0. ...
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... NXP Semiconductors Table 26. CLKOUT clock source select register (CLKOUTCLKSEL, address 0x4004 80E0) bit description Bit Symbol 1:0 SEL 31:2 - 4.5.20 CLKOUT clock source update enable register This register updates the clock source of the CLKOUT pin with the new clock after the CLKOUTCLKSEL register has been written to ...
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... NXP Semiconductors Table 29. POR captured PIO status registers 0 (PIOPORCAP0, address 0x4004 8100) bit description Bit Symbol 31:0 PIOSTAT 4.5.23 POR captured PIO status register 1 The PIOPORCAP1 register captures the state (HIGH or LOW) of the PIO pins of port 2 (PIO2_8 to PIO2_11) at power-on-reset. Each bit represents the reset state of one PIO pin ...
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... NXP Semiconductors Table 32. BOD control register (BODCTRL, address 0x4004 8150) bit description Bit Symbol 1:0 BODRSTLEV 3:2 BODINTVAL 4 BODRSTENA 31:5 - 4.5.26 System tick counter calibration register This register determines the value of the SYST_CALIB register (see Table 33. System tick timer calibration register (SYSTCKCAL, address 0x4004 8154) bit ...
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... NXP Semiconductors Table 34. AHB matrix master priority register (AHBPRIO, address 0x4004 8158) bit description Bit Symbol 1:0 M0PRIO 3:2 DMAPRIO 5:4 - 31:6 - 4.5.28 IRQ latency register The IRQLATENCY register is an eight-bit register which specifies the minimum number of cycles (0-255) permitted for the system to respond to an interrupt request. The intent of this register is to allow the user to select a trade-off between interrupt response time and determinism ...
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... NXP Semiconductors Table 36. NMI interrupt source configuration register (INTNMI, address 0x4004 8174) bit description Bit Symbol 5:0 NMISRC 31:6 - 4.5.30 Start logic edge control register 0 The STARTAPRP0 register controls the start logic inputs of ports 0 (PIO0_0 to PIO0_11). This register selects a falling or rising edge on the corresponding PIO input to produce a ...
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... NXP Semiconductors Table 37. Start logic edge control register 0 (STARTAPRP0, address 0x4004 8200) bit description Bit Symbol 3 APRPIO0_3 4 APRPIO0_4 5 APRPIO0_5 6 APRPIO0_6 7 APRPIO0_7 8 APRPIO0_8 9 APRPIO0_9 10 APRPIO0_10 11 APRPIO0_11 31:12 - 4.5.31 Start logic signal enable register 0 This STARTERP0 register enables or disables the start signal bits in the start logic. The bit assignment is identical to Table 38 ...
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... NXP Semiconductors Table 38. Start logic signal enable register 0 (STARTERP0, address 0x4004 8204) bit description Bit Symbol 3 ERPIO0_3 4 ERPIO0_4 5 ERPIO0_5 6 ERPIO0_6 7 ERPIO0_7 8 ERPIO0_8 9 ERPIO0_9 10 ERPIO0_10 11 ERPIO0_11 31:12 - 4.5.32 Start logic reset register 0 Writing a one to a bit in the STARTRSRP0CLR register resets the start logic state. The bit assignment is identical to clock edge for registering a start signal ...
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... NXP Semiconductors Table 39. Start logic reset register 0 (STARTRSRP0CLR, address 0x4004 8208) bit description Bit Symbol 0 RSRPIO0_0 1 RSRPIO0_1 2 RSRPIO0_2 3 RSRPIO0_3 4 RSRPIO0_4 5 RSRPIO0_5 6 RSRPIO0_6 7 RSRPIO0_7 8 RSRPIO0_8 9 RSRPIO0_9 10 RSRPIO0_10 11 RSRPIO0_11 31:12 - 4.5.33 Start logic status register 0 This register reflects the status of the enabled start signal bits. The bit assignment is ...
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... NXP Semiconductors Table 40. Start logic status register 0 (STARTSRP0, address 0x4004 820C) bit description Bit Symbol 0 SRPIO0_0 1 SRPIO0_1 2 SRPIO0_2 3 SRPIO0_3 4 SRPIO0_4 5 SRPIO0_5 6 SRPIO0_6 7 SRPIO0_7 8 SRPIO0_8 9 SRPIO0_9 10 SRPIO0_10 11 SRPIO0_11 31:12 - 4.5.34 Start logic edge control register 1 The STARTAPRP1 register controls the start logic inputs which are connected to the peripheral interrupts ...
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... NXP Semiconductors Table 41. Start logic bit connection to peripheral interrupts Start logic bit UM10441 User manual Chapter 4: LPC122x System control (SYSCON) Interrupt Description (state change) CT16B0 Match n Capture n CT16B1 Match n Capture n CT32B0 Match n Capture n CT32B1 Match n Capture n SSP Tx FIFO half empty Rx FIFO half full ...
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... NXP Semiconductors Table 42. Start logic edge control register 1 (STARTAPRP1, address 0x4004 8210) bit description Bit Symbol 0 APRI2C 1 APRCT16B0 2 APRCT16B1 3 APRCT32B0 4 APRCT32B1 5 APRSSP 6 APRUART0 7 APRUART1 8 APRPIOADC 9 APRCOMP 10 APRWDT 11 APRBOD APRGPIO0 14 APRGPIO1 15 APRGPIO2 16 - UM10441 User manual Chapter 4: LPC122x System control (SYSCON) Description Edge select for start logic interrupt I2C. ...
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... NXP Semiconductors Table 42. Start logic edge control register 1 (STARTAPRP1, address 0x4004 8210) bit description Bit Symbol 17 APRDMA 18 APRRTC 31:19 - 4.5.35 Start logic signal enable register 1 This STARTERP1 register enables or disables the start signal bits in the start logic. The bit assignment is identical to Table 43 ...
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... NXP Semiconductors Table 43. Start logic signal enable register 1 (STARTERP1, address 0x4004 8214) bit description Bit Symbol 10 ERWDT 11 ERBOD ERGPIO0 14 ERGPIO1 15 ERGPIO2 ERDMA 18 ERRTC 31:19 - 4.5.36 Start logic reset register 1 Writing a one to a bit in the STARTRSRP1CLR register resets the start logic state. The bit assignment is identical to clock edge for registering a start signal ...
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... NXP Semiconductors Table 44. Start logic reset register 1 (STARTRSRP1CLR, address 0x4004 8218) bit description Bit Symbol 3 RSRCT32B0 4 RSRCT32B1 5 RSRSSP 6 RSRUART0 7 RSRUART1 8 RSRADC 9 RSRCOMP 10 RSRWDT 11 RSRBOD RSRGPIO0 14 RSRGPIO1 15 RSRGPIO2 RSRDMA 18 RSRRTC 31:19 - UM10441 User manual Chapter 4: LPC122x System control (SYSCON) …continued Description Start signal reset for start logic interrupt CT32B0. ...
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... NXP Semiconductors 4.5.37 Start logic status register 1 This register reflects the status of the enabled start signals. The bit assignment is identical to Table 42. Table 45. Start logic signal status register 1 (STARTSRP1, address 0x4004 821C) bit description Bit Symbol 0 SRI2C 1 SRCT16B0 2 SRCT16B1 3 SRCT32B0 4 SRCT32B1 5 SRSSP ...
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... NXP Semiconductors Table 45. Start logic signal status register 1 (STARTSRP1, address 0x4004 821C) bit description Bit Symbol 15 SRGPIO2 SRDMA 18 SRRTC 31:19 - 4.5.38 Deep-sleep mode configuration register This register controls the behavior of the WatchDog (WD) oscillator and the BOD circuit when the device enters Deep-sleep mode. In addition, the WD oscillator behavior is influenced by the WDLOCKCLK bit in the WDMODE register blocks are shut down in Deep-sleep mode ...
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... NXP Semiconductors frequency must be set to its lowest value (bits FREQSEL in the WDTOSCCTRL = 0001, see disabled in the SYSAHBCLKCTRL register (see mode. Note that the WD oscillator must be running before setting the WDLOCKCLK bit in the WDMODE register. The watchdog oscillator, if running, contributes an additional current drain in Deep-sleep mode ...
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... NXP Semiconductors Table 49. Wake-up configuration register (PDAWAKECFG, address 0x4004 8234) bit description Bit Symbol 0 IRCOUT_PD 1 IRC_PD 2 FLASH_PD 3 BOD_PD 4 ADC_PD 5 SYSOSC_PD 6 WDTOSC_PD 7 SYSPLL_PD 14: COMP_PD 31:16 - 4.5.40 Power-down configuration register The bits in the PDRUNCFG register control the power to the various analog blocks. This register can be written to at any time while the microcontroller is running, and a write will take effect immediately with the exception of the power-down signal to the IRC ...
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... NXP Semiconductors To avoid glitches when powering down the IRC, the IRC clock is automatically switched off at a clean point. Therefore, for the IRC a delay is possible before the power-down state takes effect. Remark: Settings in this register are affected by the WDT lock status: • ...
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... NXP Semiconductors Table 50. Power-down configuration register (PDRUNCFG, address 0x4004 8238) bit description Bit Symbol 15 COMP_PD 31:16 - 4.5.41 Device ID register This device ID register is a read-only register and contains the device ID for each LPC122x part. This register is also read by the ISP/IAP commands (see ...
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... NXP Semiconductors 4.6 Reset Reset has four sources on the LPC122x: the RESET pin, Watchdog Reset, Power-On Reset (POR), and Brown Out Detect (BOD). In addition, there is a software reset. The RESET pin is a Schmitt trigger input pin. Assertion of Reset by any source, once the ...
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... NXP Semiconductors • The clock source for the system clock can be selected from the IRC (default), the system oscillator, or the watchdog oscillator (see • The system clock frequency can be selected by the SYSPLLCTRL SYSAHBCLKDIV register • Selected peripherals (UART, SSP0/1, WDT) use individual peripheral clocks with their own clock dividers ...
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... NXP Semiconductors Deep-sleep mode eliminates all power used by the flash, analog peripherals and all dynamic power used by the processor itself, memory systems and their related controllers, and internal buses. The processor state and registers, peripheral registers, and internal SRAM values are maintained, and the logic levels of the pins remain static. ...
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... NXP Semiconductors 4.7.3.3 Wake-up from Deep-sleep mode The microcontroller can wake up from Deep-sleep mode in the following ways: • Signal on an external pin. For this purpose, pins PIO0_0 to PIO0_11 can be enabled as inputs to the start logic. The start logic does not require any clocks and generates the interrupt if enabled in the NVIC to wake up from Deep-sleep mode. • ...
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... NXP Semiconductors 2. Store data to be retained in the general purpose registers 3. Write one to the SLEEPDEEP bit in the ARM Cortex-M0 SCR register 4. Ensure that the IRC is powered by setting bits IRCOUT_PD and IRC_PD to zero in the PDRUNCFG register before entering Deep power-down mode. 5. Use the ARM WFI instruction. ...
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... NXP Semiconductors 4.8.3 Using the RTC to wake up from Deep-sleep mode (start logic 1) The RTC is clocked by the independent RTC oscillator and continues to run in Deep-sleep mode. The RTC interrupt is internally connected to bit 18 in the start logic 1 block and can serve as wake-up interrupt. The user must program the start logic 1 registers for the RTC interrupt to enable the RTC wake-up and select the rising edge configuration ...
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... NXP Semiconductors – The PMU will turn on the on-chip voltage regulator. When the core voltage reaches the power-on-reset (POR) trip point, a system reset will be triggered and the microcontroller re-boots. – All registers except the GPREG0 to GPREG3 will be in their reset state. ...
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... NXP Semiconductors create the output clock(s), or are sent directly to the output(s). The main output clock is then divided the programmable feedback divider to generate the feedback clock. The output signal of the phase-frequency detector is also monitored by the lock detector, to signal when the PLL has locked on to the input clock. ...
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... NXP Semiconductors 4.10.4 Frequency selection The PLL frequency equations use the following parameters (also see Table 53. PLL frequency parameters Parameter FCLKIN FCCO FCLKOUT P M 4.10.4.1 Normal mode In normal mode the post divider is enabled, giving a 50% duty cycle clock with the following frequency relations: To select the appropriate values for M and recommended to follow these steps: 1 ...
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UM10441 Chapter 5: LPC122x Power Monitor Unit (PMU) Rev. 1.1 — 10 March 2011 5.1 How to read this chapter The PMU is identical on all LPC122x parts. 5.2 Introduction The PMU controls the Deep power-down mode. Four general purpose ...
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... NXP Semiconductors Table 56. Power control register (PCON, address 0x4003 8000) bit description Bit Symbol 8 SLEEPFLAG 10 DPDFLAG 31:12 - 5.3.2 General purpose registers The general purpose registers retain data through the Deep power-down mode when power is still applied to the V Only a “cold” boot when all power has been completely removed from the chip will reset the general purpose registers ...
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... NXP Semiconductors Table 58. System configuration register (SYSCFG, address 0x4003 8014) bit description Bit Symbol 9 WAKEUPHYS 14:11 RTCCLK 31:15 - UM10441 User manual Chapter 5: LPC122x Power Monitor Unit (PMU) Value Description - Reserved. Do not write ones to this bit. WAKEUP pin hysteresis enable 0 Hysteresis for WAKUP pin disabled. ...
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UM10441 Chapter 6: LPC122x I/O configuration (IOCONFIG) Rev. 1.1 — 10 March 2011 6.1 How to read this chapter Each pin has one IOCON register assigned. IOCON registers for pins not available are reserved (see available on 64-pin packages. Table ...
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... NXP Semiconductors 6.3.3 Pin drive Two levels of output drive can be selected for each normal-drive pin, named low mode and high mode. Four pins (PIO0_27, PIO0_28, PIO0_29, PIO0_12) are designated high-drive pins with a high mode and low mode output drive. For details see the LPC122x data sheet ...
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... NXP Semiconductors If the sensitivity to noise spikes must be minimized, select a slower PCLK and lower sample mode. 6.4 Register description Table 60 shows the IOCONFIG registers. Each multiplexed pin is associated with one register which allows to program its function and electrical characteristics. The register name is derived from the pin’s default function after reset. Note that some pins reset to functions other than GPIO. The corresponding registers are indicated by a prefix reflecting the pin’ ...
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... NXP Semiconductors Table 60. Register overview: I/O configuration block (base address 0x4004 4000) Name Access Address offset PIO0_6 R/W 0x060 PIO0_7 R/W 0x064 PIO0_8 R/W 0x068 PIO0_9 R/W 0x06C PIO2_0 R/W 0x070 PIO2_1 R/W 0x074 PIO2_2 R/W 0x078 PIO2_3 R/W 0x07C PIO2_4 ...
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... NXP Semiconductors 6.4.1 Pin configuration registers Table 61 shows the register bit allocation for all IOCON registers (except PIO0_10 and PIO0_11). Table 62 configure a true open-drain mode to comply with the full I Table 61. IOCON register bit allocation (except I Bit Symbol 2:0 FUNC MODE INV ...
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... NXP Semiconductors Table 61. IOCON register bit allocation (except I Bit Symbol 15:13 CLK_DIV 31:16 - Table 62. IOCON register bit allocation (I Bit Symbol 2:0 FUNC 5 INV 9 TOD 12:11 S_MODE UM10441 User manual Chapter 6: LPC122x I/O configuration (IOCONFIG) 2 C-pins) Value Description Select peripheral clock divider for input filter sampling clock. ...
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... NXP Semiconductors Table 62. IOCON register bit allocation (I Bit Symbol 15:13 CLK_DIV 31:16 - 6.4.2 PIO0_19 register Table 63. PIO0_19 register (PIO0_19, address 0x4004 4008) bit description Bit Symbol 2:0 FUNC MODE INV 7 ADMODE DRV 10 OD UM10441 User manual Chapter 6: LPC122x I/O configuration (IOCONFIG) ...
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... NXP Semiconductors Table 63. PIO0_19 register (PIO0_19, address 0x4004 4008) bit description Bit Symbol 12:11 S_MODE 15:13 CLK_DIV 31:16 - 6.4.3 PIO0_20 register Table 64. PIO0_20 register (PIO0_20, address 0x4004 400C) bit description Bit Symbol 2:0 FUNC MODE INV 7 ADMODE DRV UM10441 User manual ...
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... NXP Semiconductors Table 64. PIO0_20 register (PIO0_20, address 0x4004 400C) bit description Bit Symbol 10 OD 12:11 S_MODE 15:13 CLK_DIV 31:16 - 6.4.4 PIO0_21 register Table 65. PIO0_21 register (PIO0_21, address 0x4004 4010) bit description Bit Symbol 2:0 FUNC MODE INV 7 ADMODE 8 - UM10441 User manual ...
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... NXP Semiconductors Table 65. PIO0_21 register (PIO0_21, address 0x4004 4010) bit description Bit Symbol 9 DRV 10 OD 12:11 S_MODE 15:13 CLK_DIV 31:16 - 6.4.5 PIO0_22 register Table 66. PIO0_22 register (PIO0_22, address 0x4004 4014) bit description Bit Symbol 2:0 FUNC MODE INV UM10441 User manual ...
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... NXP Semiconductors Table 66. PIO0_22 register (PIO0_22, address 0x4004 4014) bit description …continued Bit Symbol 7 ADMODE DRV 10 OD 12:11 S_MODE 15:13 CLK_DIV 31:16 - 6.4.6 PIO0_23 register Table 67. PIO0_23 register (PIO0_23, address 0x4004 4018) bit description Bit Symbol 2:0 FUNC MODE UM10441 User manual ...
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... NXP Semiconductors Table 67. PIO0_23 register (PIO0_23, address 0x4004 4018) bit description Bit Symbol INV 7 ADMODE DRV 10 OD 12:11 S_MODE 15:13 CLK_DIV 31:16 - 6.4.7 PIO0_24 register Table 68. PIO0_24 register (PIO0_24, address 0x4004 401C) bit description Bit Symbol 2:0 FUNC 3 - UM10441 User manual ...
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... NXP Semiconductors Table 68. PIO0_24 register (PIO0_24, address 0x4004 401C) bit description Bit Symbol 4 MODE INV 7 ADMODE DRV 10 OD 12:11 S_MODE 15:13 CLK_DIV 31:16 - UM10441 User manual Chapter 6: LPC122x I/O configuration (IOCONFIG) Value Description Selects function mode (on-chip pull-up resistor control). 0 Inactive (pull-up resistor not enabled). ...
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... NXP Semiconductors 6.4.8 SWDIO_PIO0_25 register Table 69. SWDIO_PIO0_25 register (SWDIO_PIO0_25, address 0x4004 4020) bit description Bit Symbol 2:0 FUNC MODE INV 7 ADMODE DRV 10 OD 12:11 S_MODE UM10441 User manual Chapter 6: LPC122x I/O configuration (IOCONFIG) Value Description Selects pin function. 0x0 Selects function SWDIO. ...
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... NXP Semiconductors Table 69. SWDIO_PIO0_25 register (SWDIO_PIO0_25, address 0x4004 4020) bit description …continued Bit Symbol 15:13 CLK_DIV 31:16 - 6.4.9 SWCLK_PIO0_26 register Table 70. SWCLK_PIO0_26 register (SWCLK_PIO0_26, address 0x4004 4024) bit description Bit Symbol 2:0 FUNC MODE INV 7 ADMODE DRV UM10441 User manual Chapter 6: LPC122x I/O configuration (IOCONFIG) ...
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... NXP Semiconductors Table 70. SWCLK_PIO0_26 register (SWCLK_PIO0_26, address 0x4004 4024) bit description Bit Symbol 10 OD 12:11 S_MODE 15:13 CLK_DIV 31:16 - 6.4.10 PIO0_27 register Table 71. PIO0_27 register (PIO0_27, address 0x4004 4028) bit description Bit Symbol 2:0 FUNC MODE INV DRV UM10441 User manual ...
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... NXP Semiconductors Table 71. PIO0_27 register (PIO0_27, address 0x4004 4028) bit description …continued Bit Symbol 10 OD 12:11 S_MODE 15:13 CLK_DIV 31:16 - 6.4.11 PIO2_12 register Table 72. PIO2_12 register (PIO2_12, address 0x4004 402C) bit description Bit Symbol 2:0 FUNC MODE INV UM10441 User manual ...
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... NXP Semiconductors Table 72. PIO2_12 register (PIO2_12, address 0x4004 402C) bit description Bit Symbol 9 DRV 10 OD 12:11 S_MODE 15:13 CLK_DIV 31:16 - 6.4.12 PIO2_13 register Table 73. PIO2_13 register (PIO2_13, address 0x4004 4030) bit description Bit Symbol 2:0 FUNC MODE INV 7 - UM10441 User manual ...
Page 76
... NXP Semiconductors Table 73. PIO2_13 register (PIO2_13, address 0x4004 4030) bit description …continued Bit Symbol DRV 10 OD 12:11 S_MODE 15:13 CLK_DIV 31:16 - 6.4.13 PIO2_14 register Table 74. PIO2_14 register (PIO2_14, address 0x4004 4034) bit description Bit Symbol 2:0 FUNC MODE INV UM10441 User manual ...
Page 77
... NXP Semiconductors Table 74. PIO2_14 register (PIO2_14, address 0x4004 4034) bit description Bit Symbol 9 DRV 10 OD 12:11 S_MODE 15:13 CLK_DIV 31:16 - 6.4.14 PIO2_15 register Table 75. PIO2_15 register (PIO2_15, address 0x4004 4038) bit description Bit Symbol 2:0 FUNC MODE INV UM10441 User manual ...
Page 78
... NXP Semiconductors Table 75. PIO2_15 register (PIO2_15, address 0x4004 4038) bit description …continued Bit Symbol 9 DRV 10 OD 12:11 S_MODE 15:13 CLK_DIV 31:16 - 6.4.15 PIO0_28 register Table 76. PIO0_28 register (PIO0_28, address 0x4004 403C) bit description Bit Symbol 2:0 FUNC MODE INV UM10441 User manual ...
Page 79
... NXP Semiconductors Table 76. PIO0_28 register (PIO0_28, address 0x4004 403C) bit description Bit Symbol DRV 10 OD 12:11 S_MODE 15:13 CLK_DIV 31:16 - 6.4.16 PIO0_29 register Table 77. PIO0_29 register (PIO0_29, address 0x4004 4040) bit description Bit Symbol 2:0 FUNC MODE 5 - UM10441 User manual Chapter 6: LPC122x I/O configuration (IOCONFIG) ...
Page 80
... NXP Semiconductors Table 77. PIO0_29 register (PIO0_29, address 0x4004 4040) bit description Bit Symbol 6 INV DRV 10 OD 12:11 S_MODE 15:13 CLK_DIV 31:16 - 6.4.17 PIO0_0 register Table 78. PIO0_0 register (PIO0_0, address 0x4004 4044) bit description Bit Symbol 2:0 FUNC MODE 5 - UM10441 User manual ...
Page 81
... NXP Semiconductors Table 78. PIO0_0 register (PIO0_0, address 0x4004 4044) bit description Bit Symbol 6 INV DRV 10 OD 12:11 S_MODE 15:13 CLK_DIV 31:16 - 6.4.18 PIO0_1 register Table 79. PIO0_1 register (PIO0_1, address 0x4004 4048) bit description Bit Symbol 2:0 FUNC MODE UM10441 User manual ...
Page 82
... NXP Semiconductors Table 79. PIO0_1 register (PIO0_1, address 0x4004 4048) bit description Bit Symbol INV DRV 10 OD 12:11 S_MODE 15:13 CLK_DIV 31:16 - 6.4.19 PIO0_2 register Table 80. PIO0_2 register (PIO0_2, address 0x4004 404C) bit description Bit Symbol 2:0 FUNC 3 - UM10441 User manual Chapter 6: LPC122x I/O configuration (IOCONFIG) ...
Page 83
... NXP Semiconductors Table 80. PIO0_2 register (PIO0_2, address 0x4004 404C) bit description …continued Bit Symbol 4 MODE INV DRV 10 OD 12:11 S_MODE 15:13 CLK_DIV 31:16 - UM10441 User manual Chapter 6: LPC122x I/O configuration (IOCONFIG) Value Description Selects function mode (on-chip pull-up resistor control). 0 Inactive (pull-up resistor not enabled). ...
Page 84
... NXP Semiconductors 6.4.20 PIO0_3 register Table 81. PIO0_3 register (PIO0_3, address 0x4004 4054) bit description Bit Symbol 2:0 FUNC MODE INV DRV 10 OD 12:11 S_MODE 15:13 CLK_DIV 31:16 - UM10441 User manual Chapter 6: LPC122x I/O configuration (IOCONFIG) Value Description Selects pin function. 0x0 Selects function PIO0_3 ...
Page 85
... NXP Semiconductors 6.4.21 PIO0_4 register Table 82. PIO0_4 register (PIO0_4, address 0x4004 4058) bit description Bit Symbol 2:0 FUNC MODE INV DRV 10 OD 12:11 S_MODE 15:13 CLK_DIV 31:16 - UM10441 User manual Chapter 6: LPC122x I/O configuration (IOCONFIG) Value Description Selects pin function. 0x0 Selects function PIO0_4 ...
Page 86
... NXP Semiconductors 6.4.22 PIO0_5 register Table 83. PIO0_5 register (PIO0_5, address 0x4004 405C) bit description Bit Symbol 2:0 FUNC MODE INV DRV 10 OD 12:11 S_MODE 15:13 CLK_DIV 31:16 - UM10441 User manual Chapter 6: LPC122x I/O configuration (IOCONFIG) Value Description Selects pin function. 0x0 Selects function PIO0_5 ...
Page 87
... NXP Semiconductors 6.4.23 PIO0_6 register Table 84. PIO0_6 register (PIO0_6, address 0x4004 4060) bit description Bit Symbol 2:0 FUNC MODE INV DRV 10 OD 12:11 S_MODE 15:13 CLK_DIV 31:16 - UM10441 User manual Chapter 6: LPC122x I/O configuration (IOCONFIG) Value Description Selects pin function. 0x0 Selects function PIO0_6 ...
Page 88
... NXP Semiconductors 6.4.24 PIO0_7 register Table 85. PIO0_7 register (PIO0_7, address 0x4004 4064) bit description Bit Symbol 2:0 FUNC MODE INV DRV 10 OD 12:11 S_MODE 15:13 CLK_DIV 31:16 - UM10441 User manual Chapter 6: LPC122x I/O configuration (IOCONFIG) Value Description Selects pin function. 0x0 Selects function PIO0_7 ...
Page 89
... NXP Semiconductors 6.4.25 PIO0_8 register Table 86. PIO0_8 register (PIO0_8, address 0x4004 4068) bit description Bit Symbol 2:0 FUNC MODE INV DRV 10 OD 12:11 S_MODE 15:13 CLK_DIV 31:16 - UM10441 User manual Chapter 6: LPC122x I/O configuration (IOCONFIG) Value Description Selects pin function. 0x0 Selects function PIO0_8 ...
Page 90
... NXP Semiconductors 6.4.26 PIO0_9 register Table 87. PIO0_9 register (PIO0_9, address 0x4004 406C) bit description Bit Symbol 2:0 FUNC MODE INV DRV 10 OD 12:11 S_MODE 15:13 CLK_DIV 31:16 - UM10441 User manual Chapter 6: LPC122x I/O configuration (IOCONFIG) Value Description Selects pin function. 0x0 Selects function PIO0_9 ...
Page 91
... NXP Semiconductors 6.4.27 PIO2_0 register Table 88. PIO2_0 register (PIO2_0, address 0x4004 4070) bit description Bit Symbol 2:0 FUNC MODE INV DRV 10 OD 12:11 S_MODE 15:13 CLK_DIV 31:16 - UM10441 User manual Chapter 6: LPC122x I/O configuration (IOCONFIG) Value Description Selects pin function. 0x0 Selects function PIO2_0 ...
Page 92
... NXP Semiconductors 6.4.28 PIO2_1 register Table 89. PIO2_1 register (PIO2_1, address 0x4004 4074) bit description Bit Symbol 2:0 FUNC MODE INV DRV 10 OD 12:11 S_MODE 15:13 CLK_DIV 31:16 - UM10441 User manual Chapter 6: LPC122x I/O configuration (IOCONFIG) Value Description Selects pin function. 0x0 Selects function PIO2_1 ...
Page 93
... NXP Semiconductors 6.4.29 PIO2_2 register Table 90. PIO2_2 register (PIO2_2, address 0x4004 4078) bit description Bit Symbol 2:0 FUNC MODE INV DRV 10 OD 12:11 S_MODE 15:13 CLK_DIV 31:16 - UM10441 User manual Chapter 6: LPC122x I/O configuration (IOCONFIG) Value Description Selects pin function. 0x0 Selects function PIO2_2 ...
Page 94
... NXP Semiconductors 6.4.30 PIO2_3 register Table 91. PIO2_3 register (PIO2_3, address 0x4004 407C) bit description Bit Symbol 2:0 FUNC MODE INV DRV 10 OD 12:11 S_MODE 15:13 CLK_DIV 31:16 - UM10441 User manual Chapter 6: LPC122x I/O configuration (IOCONFIG) Value Description Selects pin function. 0x0 Selects function PIO2_3 ...
Page 95
... NXP Semiconductors 6.4.31 PIO2_4 register Table 92. PIO2_4 register (PIO2_4, address 0x4004 4080) bit description Bit Symbol 2:0 FUNC MODE INV DRV 10 OD 12:11 S_MODE 15:13 CLK_DIV 31:16 - UM10441 User manual Chapter 6: LPC122x I/O configuration (IOCONFIG) Value Description Selects pin function. 0x0 Selects function PIO2_4 ...
Page 96
... NXP Semiconductors 6.4.32 PIO2_5 register Table 93. PIO2_5 register (PIO2_5, address 0x4004 4084) bit description Bit Symbol 2:0 FUNC MODE INV DRV 10 OD 12:11 S_MODE 15:13 CLK_DIV 31:16 - UM10441 User manual Chapter 6: LPC122x I/O configuration (IOCONFIG) Value Description Selects pin function. 0x0 Selects function PIO2_5 ...
Page 97
... NXP Semiconductors 6.4.33 PIO2_6 register Table 94. PIO2_6 register (PIO2_6, address 0x4004 4088) bit description Bit Symbol 2:0 FUNC MODE INV DRV 10 OD 12:11 S_MODE 15:13 CLK_DIV 31:16 - UM10441 User manual Chapter 6: LPC122x I/O configuration (IOCONFIG) Value Description Selects pin function. 0x0 Selects function PIO2_6 ...
Page 98
... NXP Semiconductors 6.4.34 PIO2_7 register Table 95. PIO2_7 register (PIO2_7, address 0x4004 408C) bit description Bit Symbol 2:0 FUNC MODE INV DRV 10 OD 12:11 S_MODE 15:13 CLK_DIV 31:16 - UM10441 User manual Chapter 6: LPC122x I/O configuration (IOCONFIG) Value Description Selects pin function. 0x0 Selects function PIO2_7 ...
Page 99
... NXP Semiconductors 6.4.35 PIO0_10 register Table 96. PIO0_10 register (PIO0_10, address 0x4004 4090) bit description Bit Symbol 2:0 FUNC 5 INV 9 TOD 12:11 S_MODE 15:13 CLK_DIV 31:16 - 6.4.36 PIO0_11 register Table 97. PIO0_11 register (PIO0_11, address 0x4004 4094) bit description Bit Symbol 2:0 FUNC ...
Page 100
... NXP Semiconductors Table 97. PIO0_11 register (PIO0_11, address 0x4004 4094) bit description Bit Symbol 5 INV 9 TOD 12:11 S_MODE 15:13 CLK_DIV 31:16 - 6.4.37 PIO0_12 register Table 98. PIO0_12 register (PIO0_12, address 0x4004 4098) bit description Bit Symbol 2:0 FUNC MODE 5 - UM10441 User manual Chapter 6: LPC122x I/O configuration (IOCONFIG) ...
Page 101
... NXP Semiconductors Table 98. PIO0_12 register (PIO0_12, address 0x4004 4098) bit description Bit Symbol 6 INV DRV 10 OD 12:11 S_MODE 15:13 CLK_DIV 31:16 - 6.4.38 RESET_PIO0_13 register Table 99. RESET_PIO0_13 register (RESET_PIO0_13, address 0x4004 409C) bit description Bit Symbol 2:0 FUNC MODE UM10441 User manual ...
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... NXP Semiconductors Table 99. RESET_PIO0_13 register (RESET_PIO0_13, address 0x4004 409C) bit description Bit Symbol INV DRV 10 OD 12:11 S_MODE 15:13 CLK_DIV 31:16 - 6.4.39 PIO0_14 register Table 100. PIO0_14 register (PIO0_14, address 0x4004 40A0) bit description Bit Symbol 2:0 FUNC MODE UM10441 User manual ...
Page 103
... NXP Semiconductors Table 100. PIO0_14 register (PIO0_14, address 0x4004 40A0) bit description Bit Symbol INV DRV 10 OD 12:11 S_MODE 15:13 CLK_DIV 31:16 - 6.4.40 PIO0_15 register Table 101. PIO0_15 register (PIO0_15, address 0x4004 40A4) bit description Bit Symbol 2:0 FUNC 3 - UM10441 User manual ...
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... NXP Semiconductors Table 101. PIO0_15 register (PIO0_15, address 0x4004 40A4) bit description Bit Symbol 4 MODE INV DRV 10 OD 12:11 S_MODE 15:13 CLK_DIV 31:16 - UM10441 User manual Chapter 6: LPC122x I/O configuration (IOCONFIG) Value Description Selects function mode (on-chip pull-up resistor control). 0 Inactive (pull-up resistor not enabled). ...
Page 105
... NXP Semiconductors 6.4.41 PIO0_16 register Table 102. PIO0_16 register (PIO0_16, address 0x4004 40A8) bit description Bit Symbol 2:0 FUNC MODE INV DRV 10 OD 12:11 S_MODE 15:13 CLK_DIV 31:16 - UM10441 User manual Chapter 6: LPC122x I/O configuration (IOCONFIG) Value Description Selects pin function. ...
Page 106
... NXP Semiconductors 6.4.42 PIO0_17 register Table 103. PIO0_17 register (PIO0_17, address 0x4004 40AC) bit description Bit Symbol 2:0 FUNC MODE INV DRV 10 OD 12:11 S_MODE 15:13 CLK_DIV 31:16 - UM10441 User manual Chapter 6: LPC122x I/O configuration (IOCONFIG) Value Description Selects pin function. ...
Page 107
... NXP Semiconductors 6.4.43 PIO0_18 register Table 104. PIO0_18 register (PIO0_18, address 0x4004 40B0) bit description Bit Symbol 2:0 FUNC MODE INV DRV 10 OD 12:11 S_MODE 15:13 CLK_DIV 31:16 - UM10441 User manual Chapter 6: LPC122x I/O configuration (IOCONFIG) Value Description Selects pin function. ...
Page 108
... NXP Semiconductors 6.4.44 R_PIO0_30 register Table 105. R_PIO0_30 register (R_PIO0_30, address 0x4004 40B4) bit description Bit Symbol 2:0 FUNC MODE INV 7 ADMODE DRV 10 OD 12:11 S_MODE 15:13 CLK_DIV 31:16 - UM10441 User manual Chapter 6: LPC122x I/O configuration (IOCONFIG) Value Description Selects pin function. ...
Page 109
... NXP Semiconductors 6.4.45 R_PIO0_31 register Table 106. PIO0_31 register (R_PIO0_31, address 0x4004 40B8) bit description Bit Symbol 2:0 FUNC MODE INV 7 ADMODE DRV 10 OD 12:11 S_MODE 15:13 CLK_DIV 31:16 - UM10441 User manual Chapter 6: LPC122x I/O configuration (IOCONFIG) Value Description Selects pin function. ...
Page 110
... NXP Semiconductors 6.4.46 R_PIO1_0 register Table 107. R_PIO1_0 register (R_PIO1_0, address 0x4004 40BC) bit description Bit Symbol 2:0 FUNC MODE INV 7 ADMODE DRV 10 OD 12:11 S_MODE 15:13 CLK_DIV 31:16 - UM10441 User manual Chapter 6: LPC122x I/O configuration (IOCONFIG) Value Description Selects pin function. ...
Page 111
... NXP Semiconductors 6.4.47 R_PIO1_1 register Table 108. R_PIO1_1 register (R_PIO1_1, address 0x4004 40C0) bit description Bit Symbol 2:0 FUNC MODE INV 7 ADMODE DRV 10 OD 12:11 S_MODE 15:13 CLK_DIV 31:16 - UM10441 User manual Chapter 6: LPC122x I/O configuration (IOCONFIG) Value Description Selects pin function. ...
Page 112
... NXP Semiconductors 6.4.48 PIO1_2 register Table 109. PIO1_2 register (PIO1_2, address 0x4004 40C4) bit description Bit Symbol 2:0 FUNC MODE INV 7 ADMODE DRV 10 OD 12:11 S_MODE 15:13 CLK_DIV 31:16 - UM10441 User manual Chapter 6: LPC122x I/O configuration (IOCONFIG) Value Description Selects pin function. ...
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... NXP Semiconductors 6.4.49 PIO1_3 register Table 110. PIO1_3 register (PIO1_3, address 0x4004 40C8) bit description Bit Symbol 2:0 FUNC MODE INV 7 ADMODE DRV 10 OD 12:11 S_MODE 15:13 CLK_DIV 31:16 - UM10441 User manual Chapter 6: LPC122x I/O configuration (IOCONFIG) Value Description Selects pin function. This pin functions as WAKEUP pin if the part is in Deep power-down mode regardless of the value of FUNC ...
Page 114
... NXP Semiconductors 6.4.50 PIO1_4 register Table 111. PIO1_4 register (PIO1_4, address 0x4004 40CC) bit description Bit Symbol 2:0 FUNC MODE INV 7 ADMODE DRV 10 OD 12:11 S_MODE 15:13 CLK_DIV 31:16 - UM10441 User manual Chapter 6: LPC122x I/O configuration (IOCONFIG) Value Description Selects pin function. ...
Page 115
... NXP Semiconductors 6.4.51 PIO1_5 register Table 112. PIO1_5 register (PIO1_5, address 0x4004 40D0) bit description Bit Symbol 2:0 FUNC MODE INV 7 ADMODE DRV 10 OD 12:11 S_MODE 15:13 CLK_DIV 31:16 - UM10441 User manual Chapter 6: LPC122x I/O configuration (IOCONFIG) Value Description Selects pin function. ...
Page 116
... NXP Semiconductors 6.4.52 PIO1_6 register Table 113. PIO1_6 register (PIO1_6, address 0x4004 40D4) bit description Bit Symbol 2:0 FUNC MODE INV DRV 10 OD 12:11 S_MODE 15:13 CLK_DIV 31:16 - UM10441 User manual Chapter 6: LPC122x I/O configuration (IOCONFIG) Value Description Selects pin function. ...
Page 117
... NXP Semiconductors 6.4.53 PIO2_8 register Table 114. PIO2_8 register (PIO2_8, address 0x4004 40E0) bit description Bit Symbol 2:0 FUNC MODE INV DRV 10 OD 12:11 S_MODE 15:13 CLK_DIV 31:16 - UM10441 User manual Chapter 6: LPC122x I/O configuration (IOCONFIG) Value Description Selects pin function. ...
Page 118
... NXP Semiconductors 6.4.54 PIO2_9 register Table 115. PIO2_9 register (PIO2_9, address 0x4004 40E4) bit description Bit Symbol 2:0 FUNC MODE INV DRV 10 OD 12:11 S_MODE 15:13 CLK_DIV 31:16 - UM10441 User manual Chapter 6: LPC122x I/O configuration (IOCONFIG) Value Description Selects pin function. ...
Page 119
... NXP Semiconductors 6.4.55 PIO2_10 register Table 116. PIO2_10 register (PIO2_10, address 0x4004 40E8) bit description Bit Symbol 2:0 FUNC MODE INV DRV 10 OD 12:11 S_MODE 15:13 CLK_DIV 31:16 - UM10441 User manual Chapter 6: LPC122x I/O configuration (IOCONFIG) Value Description Selects pin function. ...
Page 120
... NXP Semiconductors 6.4.56 PIO2_11 register Table 117. PIO2_11 register (PIO2_11, address 0x4004 40EC) bit description Bit Symbol 2:0 FUNC MODE INV DRV 10 OD 12:11 S_MODE 15:13 CLK_DIV 31:16 - UM10441 User manual Chapter 6: LPC122x I/O configuration (IOCONFIG) Value Description Selects pin function. ...
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UM10441 Chapter 7: LPC122x Pin configuration Rev. 1.1 — 10 March 2011 7.1 General description All pins except the supply pins can have more than one function as shown in The pin function is selected through the pin’s IOCON register ...
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... NXP Semiconductors Table 118. LPC122x pin description Symbol [2] PIO0_6/RI0 CT32B1_CAP0/ CT32B1_MAT0 [2] PIO0_7/CTS0 CT32B1_CAP1/ CT32B1_MAT1 [2] PIO0_8/RXD1 CT32B1_CAP2/ CT32B1_MAT2 [2] PIO0_9/TXD1 CT32B1_CAP3/ CT32B1_MAT3 [3] PIO0_10/SCL 25 37 [3] PIO0_11/SDA CT16B0_CAP0/ CT16B0_MAT0 [7] PIO0_12/CLKOUT CT16B0_CAP1/ CT16B0_MAT1 [4] RESET/PIO0_13 28 40 [2] PIO0_14/SCK 29 41 [2] PIO0_15/SSEL CT16B1_CAP0/ CT16B1_MAT0 UM10441 User manual …continued Start Type Reset ...
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... NXP Semiconductors Table 118. LPC122x pin description Symbol [2] PIO0_16/MISO CT16B1_CAP1/ CT16B1_MAT1 [2] PIO0_17/MOSI 32 44 [2] PIO0_18/SWCLK CT32B0_CAP0/ CT32B0_MAT0 [5] PIO0_19/ACMP0_I0 CT32B0_CAP1/ CT32B0_MAT1 [5] PIO0_20/ACMP0_I1 CT32B0_CAP2/ CT32B0_MAT2 [5] PIO0_21/ACMP0_I2 CT32B0_CAP3/ CT32B0_MAT3 [5] PIO0_22/ACMP0_I3 7 7 [5] PIO0_23 ACMP1_I0/ CT32B1_CAP0/ CT32B1_MAT0 [5] PIO0_24/ACMP1_I1 CT32B1_CAP1/ CT32B1_MAT1 [5] SWDIO/ACMP1_I2 CT32B1_CAP2/ CT32B1_MAT2/ PIO0_25 UM10441 User manual … ...
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... NXP Semiconductors Table 118. LPC122x pin description Symbol [5] SWCLK/ACMP1_I3 CT32B1_CAP3/ CT32B1_MAT3/ PIO0_26 [7] PIO0_27/ACMP0_O 12 12 [7] PIO0_28/ACMP1_O CT16B0_CAP0/ CT16B0_MAT0 [7] PIO0_29/ROSC CT16B0_CAP1/ CT16B0_MAT1 [5] R/PIO0_30/AD0 34 46 [5] R/PIO0_31/AD1 35 47 PIO1_0 to PIO1_6 [5] R/PIO1_0/AD2 36 48 [5] R/PIO1_1/AD3 37 49 [5] PIO1_2/SWDIO/AD4 38 50 UM10441 User manual …continued Start Type Reset Description logic ...
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... NXP Semiconductors Table 118. LPC122x pin description Symbol [6] PIO1_3/AD5/WAKEUP 39 51 [5] PIO1_4/AD6 40 52 [5] PIO1_5/AD7 CT16B1_CAP0/ CT16B1_MAT0 [2] PIO1_6 CT16B1_CAP1/ CT16B1_MAT1 PIO2_0 to PIO2_15 [2] PIO2_0 CT16B0_CAP0/ CT16B0_MAT0/ RTS0 [2] PIO2_1 CT16B0_CAP1/ CT16B0_MAT1/RXD0 [2] PIO2_2 CT16B1_CAP0/ CT16B1_MAT0/TXD0 [2] PIO2_3 CT16B1_CAP1/ CT16B1_MAT1/DTR0 [2] PIO2_4 CT32B0_CAP0/ CT32B0_MAT0/CTS0 UM10441 User manual …continued Start ...
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... NXP Semiconductors Table 118. LPC122x pin description Symbol [2] PIO2_5 CT32B0_CAP1/ CT32B0_MAT1/RI0 [2] PIO2_6 CT32B0_CAP2/ CT32B0_MAT2/DCD0 [2] PIO2_7 CT32B0_CAP3/ CT32B0_MAT3/DSR0 [2] PIO2_8 CT32B1_CAP0/ CT32B1_MAT0 [2] PIO2_9 CT32B1_CAP1/ CT32B1_MAT1 [2] PIO2_10 CT32B1_CAP2/ CT32B1_MAT2/TXD1 [2] PIO2_11 CT32B1_CAP3/ CT32B1_MAT3/RXD1 [2] PIO2_12/RXD1 - 13 [2] PIO2_13/TXD1 - 14 [2] PIO2_14 - 15 [2] PIO2_15 - 16 RTCXIN 46 58 RTCXOUT 45 57 XTALIN ...
Page 127
... NXP Semiconductors Table 118. LPC122x pin description Symbol DD(IO DD(3V3 SSIO [1] Pin state at reset for default function Input Output internal pull-up enabled inactive, no pull-up/down enabled. [2] 3.3 V tolerant, digital I/O pin; default: pull-up enabled, no hysteresis. 2 [3] I C-bus pins tolerant; open-drain; default: no pull-up/pull-down; no hysteresis. ...
Page 128
... NXP Semiconductors Table 119. Pin multiplexing Peripheral ADC CT16B0 CT16B1 CT32B0 CT32B1 UART0 UM10441 User manual Chapter 7: LPC122x Pin configuration Function Type AD0 I AD1 I AD2 I AD3 I AD4 I AD5 I AD6 I AD7 I CT16B0_CAP0 I CT16B0_CAP1 I CT16B0_MAT0 O CT16B0_MAT1 O CT16B1_CAP0 I CT16B1_CAP1 I CT16B1_MAT0 O CT16B1_MAT1 O CT32B0_CAP0 I CT32B0_CAP1 I CT32B0_CAP2 ...
Page 129
... NXP Semiconductors Table 119. Pin multiplexing Peripheral UART1 SSP/SPI I2C SWD Reset Clockout pin [1] After reset, the SWD functions are selected by default on pins PIO0_26 and PIO0_25. UM10441 User manual Chapter 7: LPC122x Pin configuration Function Type RXD1 I TXD1 O SCK I/O MISO I/O ...
Page 130
UM10441 Chapter 8: LPC122x General Purpose I/O (GPIO) Rev. 1.1 — 10 March 2011 8.1 How to read this chapter Each pin has one bit in one of the GPIO registers assigned. GPIO registers for pins not available are reserved ...
Page 131
... NXP Semiconductors Table 121. Register overview: GPIO (base address port 0: 0x5000 0000; port 1: 0x5001 0000, port 2: 0x5002 0000) Name Access Address offset MASK R/W 0x000 PIN R 0x004 OUT R/W 0x008 SET W 0x00C CLR W 0x010 NOT W 0x014 DIR R/W 0x020 IS R/W 0x024 ...
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... NXP Semiconductors pin may have GPIO input, GPIO output, and counter/timer match output and capture input as selectable functions. Through the PIN register, the current logic state of the pin can be read in any configuration, e.g. the state of the capture input could be read exception, the pin state cannot be read if its analog function is selected (if applicable) because selecting the pin as an ADC input disconnects the digital features of the pin ...
Page 133
... NXP Semiconductors Table 125. GPIO pin output set register (SET - address 0x5000 000C (GPIO0), 0x5001 000C (GPIO1), 0x5002 000C (GPIO2)) bit description Bit Symbol 31:0 SET 8.3.5 GPIO pin output clear register This register is used to produce a LOW level output at the port pins configured as GPIO ...
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... NXP Semiconductors 8.3.7 GPIO data direction register Table 128. GPIO data direction register (DIR - address 0x5000 0020 (GPIO0), 0x5001 0020 (GPIO1), 0x5002 0020 (GPIO2)) bit description Bit Symbol 31:0 IO 8.3.8 GPIO interrupt sense register Table 129. GPIO interrupt sense register (IS - address 0x5000 0024 (GPIO0), 0x5001 0024 ...
Page 135
... NXP Semiconductors Table 132. GPIO interrupt mask register (IE - address 0x5000 0030, 0x5001 0030 (GPIO1), 0x5002 0030 (GPIO2)) bit description Bit Symbol Description 31:0 MASK 8.3.12 GPIO raw interrupt status register Bits read HIGH in the IRS register reflect the raw (prior to masking) interrupt status of the corresponding pins indicating that all the requirements have been met before they are allowed to trigger the IE ...
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UM10441 Chapter 9: LPC122x UART0 with modem control Rev. 1.1 — 10 March 2011 9.1 How to read this chapter UART0 is available on all LPC122x parts. 9.2 Basic configuration Clocks and power to the UART0 block are controlled by: ...
Page 137
... NXP Semiconductors 9.5 Register description The UART contains registers organized as shown in Bit (DLAB) is contained in LCR[7] and enables access to the Divisor Latches. Table 137. Register overview: UART0 (base address: 0x4000 8000) Name Access Address Description offset RBR RO 0x000 Receiver Buffer Register. Contains the next received character to be read. ...
Page 138
... NXP Semiconductors 9.5.1 UART Receiver Buffer Register (when DLAB = 0, Read Only) The RBR is the top byte of the UART RX FIFO. The top byte of the RX FIFO contains the oldest character received and can be read via the bus interface. The LSB (bit 0) represents the “oldest” received data bit. If the character received is less than 8 bits, the unused MSBs are padded with zeroes ...
Page 139
... NXP Semiconductors Table 140. UART Divisor Latch LSB Register (DLL - address 0x4000 8000 when DLAB = 1) bit description Bit Symbol 7:0 DLLSB 31:8 - Table 141. UART Divisor Latch MSB Register (DLM - address 0x4000 8004 when DLAB = 1) bit description Bit Symbol 7:0 DLMSB 31 ...
Page 140
... NXP Semiconductors 9.5.5 UART Interrupt Identification Register The IIR provides a status code that denotes the priority and source of a pending interrupt. The interrupts are frozen during an IIR access interrupt occurs during an IIR access, the interrupt is recorded for the next IIR access. ...
Page 141
... NXP Semiconductors The UART RDA interrupt (IIR[3:1] = 010) shares the second level priority with the CTI interrupt (IIR[3:1] = 110). The RDA is activated when the UART RX FIFO reaches the trigger level defined in FCR7:6 and is reset when the UART RX FIFO depth falls below the trigger level ...
Page 142
... NXP Semiconductors the last THRE = 1 event. This delay is provided to give the CPU time to write data to THR without a THRE interrupt to decode and service. A THRE interrupt is set immediately if the UART THR FIFO has held two or more characters at one time and currently, the THR is empty ...
Page 143
... NXP Semiconductors 9.5.6.1.1 UART receiver DMA In DMA mode, the receiver DMA request is asserted when the receiver FIFO level is equal to or greater than trigger level character time-out occurs. See the description of the RX Trigger Level above. The receiver DMA request is cleared by the DMA controller. ...
Page 144
... NXP Semiconductors Table 147. UART Modem Control Register (MCR - address 0x4000 8010) bit description Bit Symbol 0 DTRCTR L 1 RTSCTR L 3 LMS RTSEN 7 CTSEN 31:8 - 9.5.8.1 Auto-flow control If auto-RTS mode is enabled the UART receiver FIFO hardware controls the RTS output of the UART. If the auto-CTS mode is enabled the UART TSR hardware will only start transmitting if the CTS input signal is asserted ...
Page 145
... NXP Semiconductors If Auto-RTS mode is disabled, the RTSen bit controls the RTS output of the UART. If Auto-RTS mode is enabled, hardware controls the RTS output, and the actual value of RTS will be copied in the RTS Control bit of the UART. As long as Auto-RTS is enabled, the value of the RTS Control bit is read-only for software. ...
Page 146
... NXP Semiconductors The auto-CTS function reduces interrupts to the host system. When flow control is enabled, a CTS state change does not trigger host interrupts because the device automatically controls its own transmitter. Without Auto-CTS, the transmitter sends any data present in the transmit FIFO and a receiver overrun error can result. ...
Page 147
... NXP Semiconductors Table 149. UART Line Status Register (LSR - address 0x4000 8014, Read Only) bit description Bit Symbol THRE 6 TEMT 7 RXFE 31:8 - 9.5.10 UART Modem Status Register The MSR is a read-only register that provides status information on the modem input signals. MSR[3:0] is cleared on MSR read. Note that modem signals have no direct effect on the UART operation ...
Page 148
... NXP Semiconductors Table 150: UART Modem Status Register (MSR - address 0x4000 8018) bit description Bit Symbol 0 DCTS 1 DDSR 2 TERI 3 DDCD 4 CTS 5 DSR DCD 31:8 - 9.5.11 UART Scratch Pad Register The SCR has no effect on the UART operation. This register can be written and/or read at user’ ...
Page 149
... NXP Semiconductors Table 152. Auto-baud Control Register (ACR - address 0x4000 8020) bit description Bit Symbol 0 START 1 MODE 2 AUTORESTART 7 ABEOINTCLR 9 ABTOINTCLR 31:10 - 9.5.12.1 Auto-baud The UART auto-baud function can be used to measure the incoming baud-rate based on the ”AT" protocol (Hayes command). If enabled the auto-baud feature will measure the bit time of the receive data stream and set the divisor latch registers DLM and DLL accordingly ...
Page 150
... NXP Semiconductors The ACR AutoRestart bit can be used to automatically restart baud-rate measurement if a time-out occurs (the rate measurement counter overflows). If this bit is set the rate measurement will restart at the next falling edge of the UART RX pin. The auto-baud function can generate two interrupts. ...
Page 151
... NXP Semiconductors 5. If Mode = 0 then the rate counter will stop on next falling edge of the UART RX pin. If Mode = 1 then the rate counter will stop on the next rising edge of the UART RX pin. 6. The rate counter is loaded into DLM/DLL and the baud-rate will be switched to normal operation. After setting the DLM/DLL the end of auto-baud interrupt IIR ABEOInt will be set, if enabled. The RSR will now continue receiving the remaining bits of the ” ...
Page 152
... NXP Semiconductors Table 153. UART Fractional Divider Register (FDR - address 0x4000 8028) bit description Bit Function 3:0 DIVADDVAL 7:4 MULVAL 31:8 - This register controls the clock pre-scaler for the baud rate generation. The reset value of the register keeps the fractional capabilities of UART disabled making sure that UART is fully software and hardware compatible with UARTs not equipped with this feature ...
Page 153
... NXP Semiconductors Pick another FR the range [1.1, 1.9] Fig 8. Algorithm for setting UART dividers UM10441 User manual Chapter 9: LPC122x UART0 with modem control Calculating UART baudrate (BR) PCLK PCLK/(16 x BR) est est integer? False FR = 1.5 est from est DL = Int(PCLK/( est FR = PCLK/( est False 1.1 < ...
Page 154
... NXP Semiconductors Table 154. Fractional Divider setting look-up table FR DivAddVal/ MulVal 1.000 0/1 1.067 1/15 1.071 1/14 1.077 1/13 1.083 1/12 1.091 1/11 1.100 1/10 1.111 1/9 1.125 1/8 1.133 2/15 1.143 1/7 1.154 2/13 1.167 1/6 1.182 2/11 1.200 1/5 1 ...
Page 155
... NXP Semiconductors Although Table 155 control strongly suggested to let UART hardware implemented auto flow control features take care of this, and limit the scope of TXEn to software flow control. TER enables implementation of software and hardware flow control. When TXEn =1, UART transmitter will keep sending data as long as they are available. As soon as TXEn becomes 0, UART transmission will stop ...
Page 156
... NXP Semiconductors Table 156. UART RS485 Control register (RS485CTRL - address 0x4000 804C) bit description …continued Bit Symbol 3 SEL 4 DCTRL 5 OINV 31:6 - 9.5.16 UART RS-485 Address Match register The RS485ADRMATCH register contains the address match value for RS-485/EIA-485 mode. Table 157. UART RS-485 Address Match register (RS485ADRMATCH - address 0x4000 8050) ...
Page 157
... NXP Semiconductors 9.5.18 RS-485/EIA-485 modes of operation The RS-485/EIA-485 feature allows the UART to be configured as an addressable slave. The addressable slave is one of multiple slaves controlled by a single master. The UART master transmitter will identify an address character by setting the parity (9th) bit to ‘1’. For data characters, the parity bit is set to ‘0’. ...
Page 158
... NXP Semiconductors Direction control, if enabled, will use the RTS pin when RS485CTRL bit 3 = ‘0’. It will use the DTR pin when RS485CTRL bit 3 = ‘1’. When Auto Direction Control is enabled, the selected pin will be asserted (driven LOW) when the CPU writes data into the TXFIFO. The pin will be de-asserted (driven HIGH) once the last bit of data has been transmitted ...
Page 159
... NXP Semiconductors The UART transmitter block, TX, accepts data written by the CPU or host and buffers the data in the UART TX Holding Register FIFO (THR). The UART TX Shift Register (TSR) reads the data stored in the THR and assembles the data to transmit via the serial output pin, TXD1 ...
Page 160
UM10441 Chapter 10: LPC122x UART1 Rev. 1.1 — 10 March 2011 10.1 How to read this chapter The UART1 is available on all LPC122x parts. 10.2 Basic configuration Clocks and power to the UART1 block are controlled by: 1. The ...
Page 161
... NXP Semiconductors Table 161. Register overview: UART0 (base address: 0x4000 C000) Name Access Address Description offset RBR RO 0x000 Receiver Buffer Register. Contains the next received character to be read. THR WO 0x000 Transmit Holding Register. The next character to be transmitted is written here. DLL ...
Page 162
... NXP Semiconductors 10.5.1 UART Receiver Buffer Register (when DLAB = 0, Read Only) The RBR is the top byte of the UART RX FIFO. The top byte of the RX FIFO contains the oldest character received and can be read via the bus interface. The LSB (bit 0) represents the “oldest” received data bit. If the character received is less than 8 bits, the unused MSBs are padded with zeroes ...
Page 163
... NXP Semiconductors Table 164. UART Divisor Latch LSB Register (DLL - address 0x4000 C000 when DLAB = 1) bit description Bit Symbol 7:0 DLLSB 31:8 - Table 165. UART Divisor Latch MSB Register (DLM - address 0x4000 C004 when DLAB = 1) bit description Bit Symbol 7:0 DLMSB 31 ...
Page 164
... NXP Semiconductors Table 166. UART Interrupt Enable Register (IER - address 0x4000 C004 when DLAB = 0) bit description Bit Symbol 9 ABTOINTEN 31:10 - 10.5.5 UART Interrupt Identification Register The IIR provides a status code that denotes the priority and source of a pending interrupt. The interrupts are frozen during an IIR access interrupt occurs during an IIR access, the interrupt is recorded for the next IIR access ...
Page 165
... NXP Semiconductors handler routine can determine the cause of the interrupt and how to clear the active interrupt. The IIR must be read in order to clear the interrupt prior to exiting the Interrupt Service Routine. The UART RLS interrupt (IIR[3:1] = 011) is the highest priority interrupt and is set whenever any one of four error conditions occur on the UART RX input: overrun error (OE), parity error (PE), framing error (FE) and break interrupt (BI) ...
Page 166
... NXP Semiconductors [3] For details see [4] For details see Transmitter Holding Register (when DLAB = 0, Write Only)” The UART THRE interrupt (IIR[3:1] = 001 third level interrupt and is activated when the UART THR FIFO is empty provided certain initialization conditions have been met. These initialization conditions are intended to give the UART THR FIFO a chance to fill up with data to eliminate many THRE interrupts from occurring at system start-up ...
Page 167
... NXP Semiconductors Table 169. UART FIFO Control Register (FCR - address 0x4000 C008, Write Only) bit description Bit Symbol 7:6 RXTL 31:8 - 10.5.6.1 DMA operation The user can optionally operate the UART transmit and/or receive using the micro DMA. The DMA mode is determined by the DMA Mode Select bit in the FCR register. This bit only has an effect when the FIFOs are enabled via the FIFO Enable bit in the FCR register ...
Page 168
... NXP Semiconductors Table 170. UART Line Control Register (LCR - address 0x4000 C00C) bit description Bit Symbol Value Description 5 DLAB 31 10.5.8 UART Line Status Register The LSR is a Read Only register that provides status information on the UART TX and RX blocks. Table 171. UART Line Status Register (LSR - address 0x4000 C014, Read Only) bit ...
Page 169
... NXP Semiconductors Table 171. UART Line Status Register (LSR - address 0x4000 C014, Read Only) bit description Bit Symbol THRE 6 TEMT 7 RXFE 31 10.5.9 UART Scratch Pad Register The SCR has no effect on the UART operation. This register can be written and/or read at user’s discretion. There is no provision in the interrupt interface that would indicate to the host that a read or write of the SCR has occurred ...
Page 170
... NXP Semiconductors Table 172. UART Scratch Pad Register (SCR - address 0x4000 C01C) bit description Bit Symbol Description 7:0 Pad 31 10.5.10 UART Auto-baud Control Register The UART Auto-baud Control Register (ACR) controls the process of measuring the incoming clock/data rate for the baud rate generation and can be read and written at user’ ...
Page 171
... NXP Semiconductors Auto-baud is started by setting the ACR Start bit. Auto-baud can be stopped by clearing the ACR Start bit. The Start bit will clear once auto-baud has finished and reading the bit will return the status of auto-baud (pending/finished). Two auto-baud measuring modes are available which can be selected by the ACR Mode bit ...
Page 172
... NXP Semiconductors 2. A falling edge on UART RX pin triggers the beginning of the start bit. The rate measuring counter will start counting UART_PCLK cycles optionally pre-scaled by the fractional baud-rate generator. 3. During the receipt of the start bit, 16 pulses are generated on the RSR baud input with the frequency of the (fractional baud-rate pre-scaled) UART input clock, guaranteeing the start bit is stored in the RSR ...
Page 173
... NXP Semiconductors start UARTn RX U0ACR start rate counter 16xbaud_rate 16 cycles b. Mode 1 (only start bit is used for auto-baud) Fig 10. Auto-baud a) mode 0 and b) mode 1 waveform 10.5.11 UART IrDA Control Register The IrDA Control Register enables and configures the IrDA mode on each UART. The value of ICR should not be changed while transmitting or receiving data, or data loss or corruption may occur ...
Page 174
... NXP Semiconductors Table 174: UART IrDA Control Register (ICR - 0x4000 C024) bit description Bit Symbol 5:3 PULSEDIV 31 The PulseDiv bits in ICR are used to select the pulse width when the fixed pulse width mode is used in IrDA mode (IrDAEn = 1 and FixPulseEn = 1). The value of these bits should be set so that the resulting pulse width is at least 1.63 µ ...
Page 175
... NXP Semiconductors Table 176. UART Fractional Divider Register (FDR - address 0x4000 C028) bit description Bit Symbol 3:0 DIVADDVAL 7:4 MULVAL 31:8 - This register controls the clock pre-scaler for the baud rate generation. The reset value of the register keeps the fractional capabilities of UART disabled making sure that UART is fully software and hardware compatible with UARTs not equipped with this feature ...
Page 176
... NXP Semiconductors Pick another FR the range [1.1, 1.9] Fig 11. Algorithm for setting UART dividers UM10441 User manual Calculating UART baudrate (BR) PCLK PCLK/(16 x BR) est est integer? False FR = 1.5 est from est DL = Int(PCLK/( est FR = PCLK/( est False 1.1 < FR < 1.9? est True ...
Page 177
... NXP Semiconductors Table 177. Fractional Divider setting look-up table FR DivAddVal/ MulVal 1.000 0/1 1.067 1/15 1.071 1/14 1.077 1/13 1.083 1/12 1.091 1/11 1.100 1/10 1.111 1/9 1.125 1/8 1.133 2/15 1.143 1/7 1.154 2/13 1.167 1/6 1.182 2/11 1.200 1/5 1 ...
Page 178
... NXP Semiconductors Although Table 178 control strongly suggested to let UART hardware implemented auto flow control features take care of this, and limit the scope of TXEn to software flow control. TER enables implementation of software and hardware flow control. When TXEn =1, UART transmitter will keep sending data as long as they are available. As soon as TXEn becomes 0, UART transmission will stop ...
Page 179
... NXP Semiconductors The UART transmitter block, TX, accepts data written by the CPU or host and buffers the data in the UART TX Holding Register FIFO (THR). The UART TX Shift Register (TSR) reads the data stored in the THR and assembles the data to transmit via the serial output pin, TXD1 ...
Page 180
UM10441 Chapter 11: LPC122x I2C-bus controller Rev. 1.1 — 10 March 2011 11.1 How to read this chapter 2 The I C-bus controller is available on all LPC122x parts. 11.2 Basic configuration The peripheral clock to the I2C block I2C_PCLK ...
Page 181
... Fig 13. I C-bus configuration 2 11.5 Fast-mode Plus Fast-Mode Plus supports a 1 Mbit/sec transfer rate to communicate with the I which NXP Semiconductors is now providing. In order to use Fast-Mode Plus, the I IOCONFIG register block, see 400 kHz and MHz may be selected, see UM10441 User manual ...
Page 182
... NXP Semiconductors 11.6 Pin description 2 Table 180. I Pin SDA SCL 2 The I C-bus pins must be configured through the IOCON_PIO0_10 IOCON_PIO0_11 2 I C-bus pins are open-drain outputs and fully compatible with the I 11.7 Register description 2 Table 181. Register overview (base address 0x4000 0000) ...
Page 183
... NXP Semiconductors 2 Table 181. Register overview (base address 0x4000 0000) Name Access Address offset ADR3 R/W 0x028 DATA_ RO 0x02C BUFFER MASK0 R/W 0x030 MASK1 R/W 0x034 MASK2 R/W 0x038 MASK3 R/W 0x03C [1] Reset value reflects the data stored in used bits only. It does not include reserved bits content. ...
Page 184
... NXP Semiconductors When I2EN is “0”, the SDA and SCL input signals are ignored, the I addressed” slave state, and the STO bit is forced to “0”. I2EN should not be used to temporarily release the C-bus status is lost. The AA flag should be used instead. ...
Page 185
... NXP Semiconductors The AA bit can be cleared by writing 1 to the AAC bit in the I2CONCLR register. When not acknowledge (HIGH level to SDA) will be returned during the acknowledge clock pulse on the SCL line on the following situations data byte has been received while the data byte has been received while the ...
Page 186
... NXP Semiconductors 2 Table 185. I Bit Symbol 0 GC 7:1 Address 31 11.7 SCL HIGH and LOW duty cycle registers (SCLH - 0x4000 0010 and I2SCLL- 0x4000 0014) 2 Table 186. I Bit Symbol 15:0 SCLH 31: Table 187. I Bit Symbol 15:0 SCLL 31:16 - 11.7.5.1 Selecting the appropriate I Software must set values for the registers I2SCLH and I2SCLL to select the appropriate data rate and duty cycle ...
Page 187
... NXP Semiconductors I2SCLL and I2SCLH values should not necessarily be the same. Software can set different duty cycles on SCL by setting these two registers. For example, the I specification defines the SCL low time and high time at different values for a Fast-mode and Fast-mode Plus ...
Page 188
... NXP Semiconductors 2 Table 190. I Bit Symbol 0 MM_ENA 1 ENA_SCL 2 MATCH_ALL Remark: The ENA_SCL and MATCH_ALL bits have no effect if the MM_ENA is ‘0’ (i.e. if the module is NOT in monitor mode). 11.7.7.1 Interrupt in Monitor mode All interrupts will occur as normal when the module is in monitor mode. This means that ...
Page 189
... NXP Semiconductors Following all of these interrupts, the processor may read the data register to see what was actually transmitted on the bus. 11.7.7.2 Loss of arbitration in Monitor mode In monitor mode, the I the bus master or issue an ACK). Some other slave on the bus will respond instead. This will most probably result in a lost-arbitration state as far as our module is concerned ...
Page 190
... NXP Semiconductors 2 Table 192. I Bit Symbol 7:0 Data 31 11.7. Mask registers (MASK[ 0x4000 00[30, 34, 38, 3C]) The four mask registers each contain seven active bits (7:1). Any bit in these registers which is set to ‘1’ will cause an automatic compare on the corresponding bit of the received address when it is compared to the I2ADDRn register associated with that mask register ...
Page 191
... NXP Semiconductors slave mode. The STA, STO and SI bits must be 0. The SI bit is cleared by writing 1 to the SIC bit in the CONCLR register. THe STA bit should be cleared after writing the slave address. Table 194. CONSET used to configure Master mode Bit 7 Symbol ...
Page 192
... NXP Semiconductors When the slave address and data direction bit have been transmitted and an acknowledge bit has been received, the SI bit is set, and the Status Register will show the status code. For master mode, the possible status codes are 0x40, 0x48, or 0x38. For slave mode, the possible status codes are 0x68, 0x78, or 0xB0 ...
Page 193
... NXP Semiconductors 11.8.3 Slave Receiver mode In the slave receiver mode, data bytes are received from a master transmitter. To initialize the slave receiver mode, write any of the Slave Address registers (ADR0-3) and Slave Mask registers (MASK0-3) and write the I Table 195. Table 195. CONSET used to configure Slave mode ...
Page 194
... NXP Semiconductors S SLAVE ADDRESS from Master to Slave from Slave to Master Fig 18. Format of Slave Transmitter mode 2 11 implementation and operation Figure 19 shows how the on-chip I describes the individual blocks. UM10441 User manual Chapter 11: LPC122x I2C-bus controller RW=1 A DATA A = Acknowledge (SDA low Not acknowledge (SDA high) ...
Page 195
... NXP Semiconductors INPUT FILTER SDA OUTPUT STAGE INPUT FILTER SCL OUTPUT STAGE status STATUS bus DECODER 2 Fig 19 serial interface block diagram 11.9.1 Input filters and output stages Input signals are synchronized with the internal clock, and spikes shorter than three clocks are filtered out. ...
Page 196
... NXP Semiconductors 11.9.2 Address Registers, ADR0 to ADR3 These registers may be loaded with the 7-bit slave address (7 most significant bits which the I C block will respond when programmed as a slave transmitter or receiver. The LSB (GC) is used to enable General Call address (0x00) recognition. When multiple slave addresses are enabled, the actual address received may be read from the DAT register at the state where the “ ...
Page 197
... NXP Semiconductors SDA line SCL line (1) Another device transmits serial data. (2) Another device overrules a logic (dotted line) transmitted this I low. Arbitration is lost, and this I (3) This I transmitted. This I the new master once it has won arbitration. Fig 20. Arbitration procedure The synchronization logic will synchronize the serial clock generator with the clock pulses on the SCL line from another device. If two or more master devices generate clock pulses, the “ ...
Page 198
... NXP Semiconductors 2 via the I C Clock Control Registers. See the description of the CSCLL and CSCLH registers for details. The output clock pulses have a duty cycle as programmed unless the bus is synchronizing with other SCL clock sources as described above. 11.9.8 Timing and control The timing and control logic generates the timing and control signals for serial byte handling ...
Page 199
... NXP Semiconductors 2 11.10 Details operating modes The four operating modes are: • Master Transmitter • Master Receiver • Slave Receiver • Slave Transmitter Data transfers in each mode of operation are shown in Figure 25, and describing the I Table 196. Abbreviations used to describe an I Abbreviation ...
Page 200
... NXP Semiconductors 11.10.1 Master Transmitter mode In the master transmitter mode, a number of data bytes are transmitted to a slave receiver (see Figure 22). Before the master transmitter mode can be entered, CON must be initialized as follows: Table 197. CONSET used to initialize Master Transmitter mode Bit 7 Symbol ...