OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 278

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

17.1 How to read this chapter
17.2 Basic configuration
17.3 Features
17.4 Description
UM10441
User manual
The WWDT is available on all LPC122x parts.
The watchdog timer is automatically enabled by the boot ROM after reset, and the user
must continue the feed sequences or disable the watchdog timer to avoid unintended
reset of the device.
The purpose of the Watchdog Timer is to reset the microcontroller within a programmable
time window if the microcontroller enters an erroneous state. When enabled, a watchdog
event will be generated if the user program fails to feed (or reload) the Watchdog within a
predetermined amount of time. The watchdog event will cause a chip reset if configured to
do so.
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UM10441
Chapter 17: LPC122x Windowed Watchdog Timer (WWDT)
Rev. 1.1 — 10 March 2011
Internally resets chip if not reloaded during the programmable time-out period.
Selectable time period from 1,024 watchdog clocks (T
million watchdog clocks (T
Programmable 24-bit timer with internal fixed prescaler.
“Safe” watchdog operation. Once enabled, requires a hardware reset or a Watchdog
reset to be disabled.
The Watchdog clock (WDCLK) source can be selected from the Internal RC oscillator
(IRC) or the WatchDog oscillator, see
timing choices for Watchdog operation under different power reduction conditions. For
increased reliability, it also provides the ability to run the Watchdog timer from an
entirely internal source that is not dependent on an external crystal and its associated
components and wiring.
Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.
Flag to indicate Watchdog reset.
Optional windowed operation requires reload to occur between a minimum and
maximum time-out period, both programmable.
Optional warning interrupt can be generated at a programmable time prior to
watchdog time-out.
The watchdog reload value can optionally be protected such that it can only be
changed after the “warning interrupt” time is reached.
The Watchdog timer can be configured to run in Deep-sleep mode.
Debug mode.
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 March 2011
WDCLK
× 2
24
Table
× 4) in increments of 4 watchdog clocks.
13. This gives a wide range of potential
WDCLK
× 256 × 4) to over 67
© NXP B.V. 2011. All rights reserved.
User manual
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