OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 158

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
9.6 Architecture
UM10441
User manual
9.5.18.4 RS485/EIA-485 driver delay time
9.5.18.5 RS485/EIA-485 output inversion
9.5.19 UART FIFO Level register
Direction control, if enabled, will use the RTS pin when RS485CTRL bit 3 = ‘0’. It will use
the DTR pin when RS485CTRL bit 3 = ‘1’.
When Auto Direction Control is enabled, the selected pin will be asserted (driven LOW)
when the CPU writes data into the TXFIFO. The pin will be de-asserted (driven HIGH)
once the last bit of data has been transmitted. See bits 4 and 5 in the RS485CTRL
register.
The RS485CTRL bit 4 takes precedence over all other mechanisms controlling the
direction control pin with the exception of loopback mode.
The driver delay time is the delay between the last stop bit leaving the TXFIFO and the
de-assertion of RTS. This delay time can be programmed in the 8-bit RS485DLY register.
The delay time is in periods of the baud clock. Any delay time from 0 to 255 bit times may
be used.
The polarity of the direction control signal on the RTS (or DTR) pins can be reversed by
programming bit 5 in the RS485CTRL register. When this bit is set, the direction control
pin will be driven to logic 1 when the transmitter has data waiting to be sent. The direction
control pin will be driven to logic 0 after the last bit of data has been transmitted.
FIFOLVL register is a Read Only register that allows software to read the current FIFO
level status. Both the transmit and receive FIFO levels are present in this register.
Table 159. UART FIFO Level register (FIFOLVL - address 0x4000 8058, Read Only) bit
The architecture of the UART is shown below in the block diagram.
The APB interface provides a communications link between the CPU or host and the
UART.
The UART receiver block, RX, monitors the serial input line, RXD, for valid input. The
UART RX Shift Register (RSR) accepts valid characters via RXD. After a valid character is
assembled in the RSR, it is passed to the UART RX Buffer Register FIFO to await access
by the CPU or host via the generic host interface.
Bit
3:0
7:4
11:8
31:12
Symbol
RXFIFILVL
-
TXFIFOLVL
-
description
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 March 2011
Description
Reflects the current level of the UART receiver FIFO.
0 = empty, 0xF = FIFO full.
Reserved. The value read from a reserved bit is not defined.
0 = empty, 0xF = FIFO full.
Reflects the current level of the UART transmitter FIFO.
Reserved. The value read from a reserved bit is not defined.
Chapter 9: LPC122x UART0 with modem control
UM10441
© NXP B.V. 2011. All rights reserved.
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Reset
value
0x00
NA
0x00
NA