OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 414

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
25.5.2.8.1 NVIC programming hints
25.5.3.1 The CMSIS mapping of the Cortex-M0 SCB registers
25.5.3.2 CPUID Register
25.5.3 System Control Block
Software uses the CPSIE i and instructions to enable and disable interrupts. The CMSIS
provides the following intrinsic functions for these instructions:
void __disable_irq(void) // Disable Interrupts
void __enable_irq(void) // Enable Interrupts
In addition, the CMSIS provides a number of functions for NVIC control, including:
Table 381. CMSIS functions for NVIC control
The input parameter IRQn is the IRQ number, see
more information about these functions, see the CMSIS documentation.
The System Control Block (SCB) provides system implementation information, and
system control. This includes configuration, control, and reporting of the system
exceptions. The SCB registers are:
Table 382. Summary of the SCB registers
[1]
To improve software efficiency, the CMSIS simplifies the SCB register presentation. In the
CMSIS, the array SHP[1] corresponds to the registers SHPR2-SHPR3.
The CPUID register contains the processor part number, version, and implementation
information. See the register summary in for its attributes. The bit assignments are:
CMSIS interrupt control function
void NVIC_EnableIRQ(IRQn_t IRQn)
void NVIC_DisableIRQ(IRQn_t IRQn)
uint32_t NVIC_GetPendingIRQ (IRQn_t IRQn)
void NVIC_SetPendingIRQ (IRQn_t IRQn)
void NVIC_ClearPendingIRQ (IRQn_t IRQn)
void NVIC_SetPriority (IRQn_t IRQn, uint32_t priority)
uint32_t NVIC_GetPriority (IRQn_t IRQn)
void NVIC_SystemReset (void)
Address
0xE000ED00
0xE000ED04
0xE000ED0C
0xE000ED10
0xE000ED14
0xE000ED1C
0xE000ED20
See the register description for more information.
Name
CPUID
ICSR
AIRCR
SCR
CCR
SHPR2
SHPR3
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 March 2011
Type
RO
RW
RW
RW
RO
RW
RW
[1]
[1]
Reset value
0x410CC200
0x00000000
0xFA050000
0x00000000
0x00000204
0x00000000
0x00000000
Chapter 25: LPC122x Appendix ARM Cortex-M0
Table 25–361
Description
Section 25.5.3.2
Section 25–25.5.3.3
Section 25–25.5.3.4
Section 25–25.5.3.5
Section 25–25.5.3.6
Section 25–25.5.3.7.1
Section 25–25.5.3.7.2
Description
Enable IRQn
Disable IRQn
Return true (1) if IRQn is pending
Set IRQn pending
Clear IRQn pending status
Set priority for IRQn
Read priority of IRQn
Reset the system
for more information. For
UM10441
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