OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 212

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
Table 203. Miscellaneous States
UM10441
User manual
Status
Code
(CSTAT)
0xF8
0x00
11.10.6.1 STAT = 0xF8
11.10.6.2 STAT = 0x00
Status of the I
and hardware
No relevant state
information available;
SI = 0.
Bus error during MST
or selected slave
modes, due to an
illegal START or
STOP condition. State
0x00 can also occur
when interference
causes the I
to enter an undefined
state.
11.10.6 Miscellaneous states
11.10.7 Some special cases
2
There are two STAT codes that do not correspond to a defined I
Table
This status code indicates that no relevant information is available because the serial
interrupt flag, SI, is not yet set. This occurs between other states and when the I
is not involved in a serial transfer.
This status code indicates that a bus error has occurred during an I
bus error is caused when a START or STOP condition occurs at an illegal position in the
format frame. Examples of such illegal positions are during the serial transfer of an
address byte, a data byte, or an acknowledge bit. A bus error may also be caused when
external interference disturbs the internal I
set. To recover from a bus error, the STO flag must be set and SI must be cleared. This
causes the I
clear the STO flag (no other bits in CON are affected). The SDA and SCL lines are
released (a STOP condition is not transmitted).
The I
during a serial transfer:
C block
•
•
•
•
•
2
C-bus
Simultaneous repeated START conditions from two masters
Data transfer after loss of arbitration
Forced access to the I
I
Bus error
2
2
C-bus obstructed by a LOW level on SCL or SDA
203). These are discussed below.
C hardware has facilities to handle the following special cases that may occur
Application software response
To/From DAT
No DAT action
No DAT action
2
C block to enter the “not addressed” slave mode (a defined state) and to
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Rev. 1.1 — 10 March 2011
2
C-bus
To CON
STA STO SI
0
No CON action
1
0
2
C block signals. When a bus error occurs, SI is
AA
X
Chapter 11: LPC122x I2C-bus controller
Next action taken by I
Wait or proceed current transfer.
Only the internal hardware is affected in
the MST or addressed SLV modes. In all
cases, the bus is released and the I
block is switched to the not addressed
SLV mode. STO is reset.
2
C hardware state (see
2
C serial transfer. A
UM10441
© NXP B.V. 2011. All rights reserved.
2
C hardware
2
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C block
2
C