OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 52

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
4.10 System PLL functional description
UM10441
User manual
Fig 4.
sys_osc_clk
irc_osc_clk
SYSPLLCLKSEL
System PLL block diagram
The LPC122x uses the system PLL to create the clocks for the core and peripherals.
The block diagram of this PLL is shown in
to 25 MHz. The input clock is fed directly to the Phase-Frequency Detector (PFD). This
block compares the phase and frequency of its inputs, and generates a control signal
when phase and/ or frequency do not match. The loop filter filters these control signals
and drives the current controlled oscillator (CCO), which generates the main clock and
optionally two additional phases. The CCO frequency range is 156 MHz to
320 MHz.These clocks are either divided by 2×P by the programmable post divider to
2. Once the microcontroller has booted, read the deep power-down flag in the PCON
3. Clear the deep power-down flag in the PCON register
4. Read the content of the General Purpose registers if needed.
5. Read the RTC count.
6. (Optional) Clear the RTC interrupt in the RTC ICR register and the pending interrupt in
7. (Optional) Read the stored data in the general purpose registers
8. Set up the PMU for the next Deep power-down cycle.
– The PMU will turn on the on-chip voltage regulator. When the core voltage reaches
– All registers except the GPREG0 to GPREG3 will be in their reset state.
– The contents of the RTC registers will be preserved.
register
power-down.
the NVIC.
Table
PFD
the power-on-reset (POR) trip point, a system reset will be triggered and the
microcontroller re-boots.
58).
(Table
analog section
DETECT
All information provided in this document is subject to legal disclaimers.
LOCK
MSEL<4:0>
/M
pd
cd
57) to verify that the reset was caused by a wake-up event from Deep
5
Rev. 1.1 — 10 March 2011
pd
LOCK
Chapter 4: LPC122x System control (SYSCON)
Figure
PSEL<1:0>
4. The input frequency range is 10 MHz
2
/2P
pd
cd
(Table
55).
(Table 57
UM10441
© NXP B.V. 2011. All rights reserved.
and
FCLKOUT
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