OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 376

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
25.4 Instruction set
UM10441
User manual
25.3.5.1.3 Sleep-on-exit
25.3.5.2.1 Wakeup from WFI or sleep-on-exit
25.3.5.2.2 Wakeup from WFE
25.3.5.2 Wakeup from sleep mode
25.3.5.3 Power management programming hints
25.4.1 Instruction set summary
If the SLEEPONEXIT bit of the SCR is set to 1, when the processor completes the
execution of an exception handler and returns to Thread mode it immediately enters sleep
mode. Use this mechanism in applications that only require the processor to run when an
interrupt occurs.
The conditions for the processor to wakeup depend on the mechanism that caused it to
enter sleep mode.
Normally, the processor wakes up only when it detects an exception with sufficient priority
to cause exception entry.
Some embedded systems might have to execute system restore tasks after the processor
wakes up, and before it executes an interrupt handler. To achieve this set the PRIMASK
bit to 1. If an interrupt arrives that is enabled and has a higher priority than current
exception priority, the processor wakes up but does not execute the interrupt handler until
the processor sets PRIMASK to zero. For more information about PRIMASK, see
Section
The processor wakes up if:
In addition, if the SEVONPEND bit in the SCR is set to 1, any new pending interrupt
triggers an event and wakes up the processor, even if the interrupt is disabled or has
insufficient priority to cause exception entry. For more information about the SCR see
Section
ISO/IEC C cannot directly generate the WFI, WFE, and SEV instructions. The CMSIS
provides the following intrinsic functions for these instructions:
void __WFE(void) // Wait for Event
void __WFI(void) // Wait for Interrupt
void __SEV(void) // Send Event
The processor implements a version of the Thumb instruction set.
supported instructions.
Remark: In
•
•
it detects an exception with sufficient priority to cause exception entry
in a multiprocessor system, another processor in the system executes a SEV
instruction.
25–25.3.1.3.6.
25–25.5.3.5.
Table 363
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 March 2011
Chapter 25: LPC122x Appendix ARM Cortex-M0
Table 363
UM10441
© NXP B.V. 2011. All rights reserved.
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