OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 190

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
11.8 I
UM10441
User manual
2
C operating modes
11.7.10 I
11.8.1 Master Transmitter mode
Table 192. I
The four mask registers each contain seven active bits (7:1). Any bit in these registers
which is set to ‘1’ will cause an automatic compare on the corresponding bit of the
received address when it is compared to the I2ADDRn register associated with that mask
register. In other words, bits in an I2ADDRn register which are masked are not taken into
account in determining an address match.
On reset, all mask register bits are cleared to ‘0’.
The mask register has no effect on comparison to the General Call address (“0000000”).
Bits(31:8) and bit(0) of the mask registers are unused and should not be written to. These
bits will always read back as zeros.
When an address-match interrupt occurs, the processor will have to read the data register
(DAT) to determine what the received address was that actually caused the match.
Table 193. I
In a given application, the I
mode, the I
address. If one of these addresses is detected, an interrupt is requested. If the processor
wishes to become the bus master, the hardware waits until the bus is free before the
master mode is entered so that a possible slave operation is not interrupted. If bus
arbitration is lost in the master mode, the I
immediately and can detect any of its own configured slave addresses in the same serial
transfer.
In this mode data is transmitted from master to slave. Before the master transmitter mode
can be entered, the CONSET register must be initialized as shown in
must be set to 1 to enable the I
acknowledge any address when another device is master of the bus, so it can not enter
Bit Symbol
7:0 Data
31:
8
Bit Symbol
0
7:1 MASK
31:
8
2
C Mask registers (MASK[0, 1, 2, 3] - 0x4000 00[30, 34, 38, 3C])
-
-
-
0x4000 0038, MASK3 - 0x4000 003C) bit description
2
2
2
C hardware looks for any one of its four slave addresses and the General Call
C Data buffer register (DATA_BUFFER - 0x4000 002C) bit description
C Mask registers (MASK0 - 0x4000 0030, MASK1 - 0x4000 0034, MASK2 -
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Description
This register holds contents of the 8 MSBs of the I2DAT shift
register.
Reserved
Description
Reserved. User software should not write ones to reserved bits.
This bit reads always back as 0.
Mask bits.
Reserved. User software should not write ones to reserved bits.
These bits read always back as 0’s.
Rev. 1.1 — 10 March 2011
2
C block may operate as a master, a slave, or both. In the slave
2
C function. If the AA bit is 0, the I
2
C block switches to the slave mode
Chapter 11: LPC122x I2C-bus controller
2
C interface will not
Table
UM10441
© NXP B.V. 2011. All rights reserved.
Reset value
0
-
Reset value
0
0x00
0
194. I2EN
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