OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 345

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
Table 345. channel_cfg bit assignments
UM10441
User manual
Bit
2:0
3
13:4
17:14
Name
cycle_ctrl
next_useburst
n_minus_1
R_power
The operating mode of the DMA cycle. The modes are:
Description
000: Stop. Indicates that the data structure is invalid.
001: Basic. The controller must receive a new request, prior to it entering the arbitration process,
to enable the DMA cycle to complete.
010: Auto-request. The controller automatically inserts a request for the appropriate channel
during the arbitration process. This means that the initial request is sufficient to enable the DMA
cycle to complete.
011: Ping-pong. The controller performs a DMA cycle using one of the data structures. After the
DMA cycle completes, it performs a DMA cycle using the other data structure. After the DMA
cycle completes and provided that the host processor has updated the original data structure, it
performs a DMA cycle using the original data structure. The controller continues to perform DMA
cycles until it either reads an invalid data structure or the host processor changes the cycle_ctrl
bits to 001 or 010.
100 - 111: not used.
Controls if the chnl_useburst_set [C] bit is set to a 1, when the controller is performing a
peripheral scatter-gather and is completing a DMA cycle that uses the alternate data structure.
See the ARM micro DMA (PL230) documentation for details.
Prior to the DMA cycle commencing, these bits represent the total number of DMA transfers that
the DMA cycle contains. These bits must be set according to the size of DMA cycle.
The 10-bit value indicates the number of DMA transfers, minus one. The possible values are:
000000000 = 1 DMA transfer
000000001 = 2 DMA transfers
000000010 = 3 DMA transfers
000000011 = 4 DMA transfers
000000100 = 5 DMA transfers
...
111111111 = 1024 DMA transfers.
The controller updates this field immediately prior to it entering the arbitration process. This
enables the controller to store the number of outstanding DMA transfers that are necessary to
complete the DMA cycle.
Set these bits to control how many DMA transfers can occur before the controller re-arbitrates.
The possible arbitration rate settings are:
0000: Arbitrates after each DMA transfer.
0001: Arbitrates after 2 DMA transfers.
0010: Arbitrates after 4 DMA transfers.
0011: Arbitrates after 8 DMA transfers.
0100: Arbitrates after 16 DMA transfers.
0101: Arbitrates after 32 DMA transfers.
0110: Arbitrates after 64 DMA transfers.
0111: Arbitrates after 128 DMA transfers.
1000: Arbitrates after 256 DMA transfers.
1001: Arbitrates after 512 DMA transfers.
1010-1111: Arbitrates after 1024 DMA transfers. This means that no arbitration occurs during the
DMA transfer because the maximum transfer size is 1024.
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 March 2011
Chapter 21: LPC122x General purpose micro DMA controller
UM10441
© NXP B.V. 2011. All rights reserved.
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