OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 182

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
11.6 Pin description
11.7 Register description
Table 181. Register overview: I
UM10441
User manual
Name
CONSET
STAT
DAT
ADR0
SCLH
I2SCLL
CONCLR
MMCTRL
ADR1
ADR2
Access Address
R/W
RO
R/W
R/W
R/W
R/W
WO
R/W
R/W
R/W
Table 180. I
The I
IOCON_PIO0_11
I
Pin
SDA
SCL
2
offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
C-bus pins are open-drain outputs and fully compatible with the I
2
C-bus pins must be configured through the IOCON_PIO0_10
2
C (base address 0x4000 0000)
2
C-bus pin description
Description
I2C Control Set Register. When a one is written to a bit of this register,
the corresponding bit in the I
no effect on the corresponding bit in the I
I2C Status Register. During I
status codes that allow software to determine the next action needed.
I2C Data Register. During master or slave transmit mode, data to be
transmitted is written to this register. During master or slave receive
mode, data that has been received may be read from this register.
I2C Slave Address Register 0. Contains the 7-bit slave address for
operation of the I
mode. The least significant bit determines whether a slave responds to
the General Call address.
SCH Duty Cycle Register High Half Word. Determines the high time of
the I
SCL Duty Cycle Register Low Half Word. Determines the low time of
the I
frequency generated by an I
mode.
I2C Control Clear Register. When a one is written to a bit of this register,
the corresponding bit in the I
has no effect on the corresponding bit in the I
Monitor mode control register.
I2C Slave Address Register 1. Contains the 7-bit slave address for
operation of the I
mode. The least significant bit determines whether a slave responds to
the General Call address.
I2C Slave Address Register 2. Contains the 7-bit slave address for
operation of the I
mode. The least significant bit determines whether a slave responds to
the General Call address.
Type
Input/Output
Input/Output
All information provided in this document is subject to legal disclaimers.
2
2
(Table
C clock.
C clock. I2nSCLL and I2nSCLH together determine the clock
Rev. 1.1 — 10 March 2011
97) registers for standard/ Fast-mode or Fast-mode Plus. The
2
2
2
C interface in slave mode, and is not used in master
C interface in slave mode, and is not used in master
C interface in slave mode, and is not used in master
Description
I
I
2
2
C Serial Data
C Serial Clock
2
2
2
C master and certain times used in slave
C control register is set. Writing a zero has
C control register is cleared. Writing a zero
2
C operation, this register provides detailed
Chapter 11: LPC122x I2C-bus controller
2
C control register.
2
C control register.
2
C-bus specification.
(Table
UM10441
© NXP B.V. 2011. All rights reserved.
96) and
Reset
value
0x00
0xF8
0x00
0x00
0x04
0x04
NA
0x00
0x00
0x00
182 of 442
[1]