OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 331

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
21.6.7 Channel useburst set register
21.6.8 Channel useburst clear register
Table 326. Channel software request register (CHNL_SW_REQUEST, address 0x4004 C014)
This register is a read/write register and disables the single DMA request (dma_sreq[c])
input for a channel c (c = 0 to 20) from generating requests. Therefore, only the
dma_req[c] signal generates requests.
Remark: The useburst status register applies to channels 4 and 5 (SSP) only.
Reading this register returns the useburst status. Writing to a bit where a DMA channel is
not implemented has no effect.
Table 327. Channel useburst set register (CHNL_USEBURST_SET, address 0x4004 C018) bit
This register is a write-only register and enables the DMA single request for a channel c
(c = 0 to 7, dma_sreq[c]) to generate requests. Writing to a bit where a DMA channel is not
implemented has no effect.
Remark: The useburst clear register applies to channels 4 and 5 (SSP) only.
Bit
20:0
31:21 -
Bit
20:0
31:21 -
Symbol
DMA_USEBURST_
SET
Symbol
DMA_SW_
REQUEST
bit description
description
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 March 2011
Description
Set the appropriate bit to generate a software DMA request on
the corresponding DMA channel.
Write as:
Bit [c] = 0: Does not create a DMA request for channel c.
Bit [c] = 1: Creates a DMA request for channel c.
Reserved.
Chapter 21: LPC122x General purpose micro DMA controller
Description
Returns the useburst status for channel c (c = 0 to 20) or
disables dma_sreq[c] from generating DMA requests. (For
channels 4 and 5 only.)
Read as:
Bit [c] = 0: DMA channel c responds to requests that it
receives on dma_req[c] or dma_sreq[c]. The controller
performs 2
Bit [c] = 1: DMA channel c does not respond to requests that
it receives on dma_sreq[c]. The controller only responds to
dma_req[c] requests and performs 2
Write as:
Bit [c] = 0: No effect. Use the CHNL_USEBURST_CLR
register to set bit [c] to 0.
Bit [c] = 1: Disables dma_sreq[C] from generating DMA
requests. The controller performs 2
Reserved.
R
, or single, bus transfers.
R
R
transfers.
transfers.
UM10441
© NXP B.V. 2011. All rights reserved.
331 of 442
Reset
value
-
-
-
Reset
value
0x0