OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 4

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
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– PLL allows CPU operation up to the maximum CPU rate without the need for a
– Clock output function with divider that can reflect the system oscillator clock, IRC
– Real-Time Clock (RTC).
Digital peripherals
– Micro DMA controller with 21 channels.
– CRC engine.
– Two UARTs with fractional baud rate generation and internal FIFO. One UART with
– SSP/SPI controller with FIFO and multi-protocol capabilities.
– I
– Up to 55 General Purpose I/O (GPIO) pins with programmable pull-up resistor,
– Programmable output drive on all GPIO pins. Four pins support high-current output
– All GPIO pins can be used as edge and level sensitive interrupt sources.
– Four general purpose counter/timers with four capture inputs and four match
– Windowed WatchDog Timer (WWDT).
Analog peripherals
– One 8-channel, 10-bit ADC.
– Two highly flexible analog comparators. Comparator outputs can be programmed
Power
– Three reduced power modes: Sleep, Deep-sleep, and Deep power-down.
– Processor wake-up from Deep-sleep mode via start logic using 12 port pins.
– Processor wake-up from Deep-power down and Deep-sleep modes via the RTC.
– Brownout detect with three separate thresholds each for interrupt and forced reset.
– Power-On Reset (POR).
– Integrated PMU (Power Management Unit).
Unique device serial number for identification.
3.3 V power supply.
Available as 64-pin and 48-pin LQFP package.
high-frequency crystal. May be run from the system oscillator or the internal RC
oscillator.
clock, main clock, and Watchdog clock.
RS-485 and modem support and one standard UART with IrDA.
data rate of 1 Mbit/s with multiple address recognition and monitor mode. I
pins have programmable glitch filter.
open-drain mode, programmable digital input glitch filter, and programmable input
inverter.
drivers.
outputs (32-bit timers) or two capture inputs and two match outputs (16-bit timers).
to trigger a timer match signal or can be used to emulate 555 timer behavior.
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C-bus interface supporting full I
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 March 2011
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C-bus specification and Fast-mode Plus with a
Chapter 1: LPC122x Introductory information
UM10441
© NXP B.V. 2011. All rights reserved.
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C-bus
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