OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 339

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
Table 341. DMA control signals
UM10441
User manual
Signal
DMA active
DMA done
Bus error
21.7.2 DMA arbitration
21.7.3 DMA priority
dma_err
Name
dma_active[c]
dma_done[c]
The controller can be configured to perform arbitration during a DMA cycle before and
after a programmable number of transfers. This reduces the latency for servicing a higher
priority channel.
The controller uses four bits in the channel control data structure (see
configure how many AHB bus transfers occur before the controller re-arbitrates. These
bits are known as the R_power bits because the value R is raised to the power of two and
this determines the arbitration rate. For example, if R = 4 then the arbitration rate is 2
that is, the controller arbitrates every 16 DMA transfers.
Remark: Do not assign a low-priority channel with a large R_power value because this
prevents the controller from servicing high-priority requests until it re-arbitrates.
When N > 2
sequences of 2
the remaining N transfers at the end of the DMA cycle.
Each channel can be configured to use either the default priority level or a high priority
level by setting the CHNL_PRIORITY_SET Register.
When the controller arbitrates, it determines the next channel to service by using the
following information:
Channel number zero has the highest priority and as the channel number increases, the
priority of a channel decreases. The controller services all enabled channels with high
priority first in increasing order of their channel number and then all channels with default
priority (see
•
•
Priority level (default or high) assigned to the channel
Channel number
Controller/
Source/
destination
Controller/
peripheral
Controller/
NVIC
NVIC
R
Table
and is not an integer multiple of 2
R
All information provided in this document is subject to legal disclaimers.
transfers until N < 2
342).
Rev. 1.1 — 10 March 2011
Chapter 21: LPC122x General purpose micro DMA controller
Description
The controller asserts the dma_active signal of a currently active
channel that is transferring data. Only one dma_active signal can be
active at any one time.
When the controller completes a DMA cycle, it asserts dma_done for a
duration of one system clock cycle. For enabled channels, only one
dma_done signal can be asserted at any one time. The DMA done
signal sets the corresponding bit in the CHNL_IRQ_STATUS register
(Table
(Table
This is the DMA interrupt signal. The controller asserts dma_err HIGH,
if an error occurs on the AHB-Lite master interface. The signal remains
HIGH until the user writes to the ERR_CLR register
dma_err signal can generate an interrupt to the NVIC if enabled in the
IRQ_ERR_ENABLE register
338) and, if enabled in the CHNL_IRQ_ENABLE register
340), will generate an interrupt to the NVIC.
R
remain to be transferred. The controller performs
R
then the controller always performs
(Table
339).
UM10441
Table
© NXP B.V. 2011. All rights reserved.
(Table
345) that
337). The
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