OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 245

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
Table 227. Capture Control Register (CCR, address 0x4001 0028 (CT16B0) and 0x4001 4028 (CT16B1)) bit
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User manual
Bit
0
1
2
3
Symbol
CAP0RE
CAP0FE
CAP0I
CAP1RE
description
13.7.7 Match Registers
13.7.8 Capture Control Register
Value Description
1
0
1
0
1
0
1
0
The Match register values are continuously compared to the Timer Counter value. When
the two values are equal, actions can be triggered automatically. The action possibilities
are to generate an interrupt, reset the Timer Counter, or stop the timer. Actions are
controlled by the settings in the MCR register.
Table 226: Match registers (MR0 to 3, addresses 0x4001 0018 to 24 (CT16B0) and
The Capture Control Register is used to control whether the Capture Register is loaded
with the value in the Counter/timer when the capture event occurs, and whether an
interrupt is generated by the capture event. Setting both the rising and falling bits at the
same time is a valid configuration, resulting in a capture event for both edges. In the
description below, "n" represents the Timer number, 0 or 1.
On the LPC122x, the capture channels 2 and 3 are connected to the edge and level
outputs of the comparators (see
the comparator number, 0 or 1. Comparator 0 is connected to CT16B0, and comparator 1
is connected to CT16B1.
Bit
15:0
31:16
Capture on CT16Bn_CAP0 rising edge: a sequence of 0 then 1 on CT16Bn_CAP0 will
cause CR0 to be loaded with the contents of TC.
Enabled.
Disabled.
Capture on CT16Bn_CAP0 falling edge: a sequence of 1 then 0 on CT16Bn_CAP0 will
cause CR0 to be loaded with the contents of TC.
Enabled.
Disabled.
Interrupt on CT16Bn_CAP0 event: a CR0 load due to a CT16Bn_CAP0 event will
generate an interrupt.
Enabled.
Disabled.
Capture on CT16Bn_CAP1 rising edge: a sequence of 0 then 1 on CT16Bn_CAP1 will
cause CR1 to be loaded with the contents of TC.
Enabled.
Disabled.
Symbol
MATCH
-
0x4001 4018 to 24 (CT16B1)) bit description
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 March 2011
Description
Timer counter match value.
Reserved.
Chapter 13: LPC122x 16-bit Counter/timer 0/1 (CT16B0/1)
Table
217). In the description below, “n” also represents
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Reset
value
0
0
0
0
Reset
value
0
-