OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 427

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
Table 106. PIO0_31 register (R_PIO0_31, address 0x4004
Table 107. R_PIO1_0 register (R_PIO1_0, address 0x4004
Table 108. R_PIO1_1 register (R_PIO1_1, address 0x4004
Table 109. PIO1_2 register (PIO1_2, address 0x4004 40C4)
Table 110. PIO1_3 register (PIO1_3, address 0x4004 40C8)
Table 111. PIO1_4 register (PIO1_4, address 0x4004 40CC)
Table 112. PIO1_5 register (PIO1_5, address 0x4004 40D0)
Table 113. PIO1_6 register (PIO1_6, address 0x4004 40D4)
Table 114. PIO2_8 register (PIO2_8, address 0x4004 40E0)
Table 115. PIO2_9 register (PIO2_9, address 0x4004 40E4)
Table 116. PIO2_10 register (PIO2_10, address 0x4004
Table 117. PIO2_11 register (PIO2_11, address 0x4004
Table 118. LPC122x pin description . . . . . . . . . . . . . . .121
Table 119. Pin multiplexing . . . . . . . . . . . . . . . . . . . . . . .127
Table 120. Available GPIO pins/ports . . . . . . . . . . . . . . .130
Table 121. Register overview: GPIO (base address port 0:
Table 122. GPIO mask register (MASK - address 0x5000
Table 123. GPIO pin value register (PIN - address 0x5000
Table 124. GPIO pin output register (OUT - address 0x5000
Table 125. GPIO pin output set register (SET - address
Table 126. GPIO pin output clear register (CLR - address
Table 127. GPIO NOT register (NOT - address 0x5000 0014
Table 128. GPIO data direction register (DIR - address
Table 129. GPIO interrupt sense register (IS - address
UM10441
User manual
0x4004 40B4) bit description . . . . . . . . . . . .108
40B8) bit description . . . . . . . . . . . . . . . . . . .109
40BC) bit description . . . . . . . . . . . . . . . . . . . 110
40C0) bit description . . . . . . . . . . . . . . . . . . . 111
bit description . . . . . . . . . . . . . . . . . . . . . . . . 112
bit description
bit description . . . . . . . . . . . . . . . . . . . . . . . . 114
bit description . . . . . . . . . . . . . . . . . . . . . . . . 115
bit description
bit description . . . . . . . . . . . . . . . . . . . . . . . . 117
bit description
40E8) bit description . . . . . . . . . . . . . . . . . . . 119
40EC) bit description . . . . . . . . . . . . . . . . . . .120
0x5000 0000; port 1: 0x5001 0000, port 2: 0x5002
0000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
0000 (GPIO0), 0x5001 0000 (GPIO1), 0x5002
0000 (GPIO2)) bit description . . . . . . . . . . . .131
0004 (GPIO0), 0x5001 0004 (GPIO1); 0x5002
0004 (GPIO2)) bit description . . . . . . . . . . . .132
0008 (GPIO0), 0x5001 0008 (GPIO1), 0x5002
0008 (GPIO2)) bit description . . . . . . . . . . . .132
0x5000 000C (GPIO0), 0x5001 000C (GPIO1),
0x5002 000C (GPIO2)) bit description . . . . . .133
0x5000 0010 (GPIO0), 0x5000 1010 (GPIO1),
0x5002 0010 (GPIO2)) bit description . . . . . .133
(GPIO0), 0x5001 0014 (GPIO1), 0x5002 0014
(GPIO2)) bit description . . . . . . . . . . . . . . . . .133
0x5000 0020 (GPIO0), 0x5001 0020 (GPIO1),
0x5002 0020 (GPIO2)) bit description . . . . . .134
0x5000 0024 (GPIO0), 0x5001 0024 (GPIO1),
0x5002 0024 (GPIO2)) bit description . . . . . .134
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 March 2011
Table 130. GPIO interrupt both edges sense register (IBE -
Table 131. GPIO interrupt event register (IEV - address
Table 132. GPIO interrupt mask register (IE - address
Table 133. GPIO raw interrupt mask status register (RIS -
Table 134. GPIO masked interrupt status register (MIS -
Table 135. GPIO interrupt clear register (IC - address 0x5000
Table 136. UART0 pin description . . . . . . . . . . . . . . . . . 136
Table 137. Register overview: UART0 (base address:
Table 138. UART Receiver Buffer Register (RBR - address
Table 139. UART Transmitter Holding Register (THR -
Table 140. UART Divisor Latch LSB Register (DLL - address
Table 141. UART Divisor Latch MSB Register (DLM -
Table 142. UART Interrupt Enable Register (IER - address
Table 143. UART Interrupt Identification Register (IIR -
Table 144. UART Interrupt Handling . . . . . . . . . . . . . . . . 141
Table 145. UART FIFO Control Register (FCR - address
Table 146. UART Line Control Register (LCR - address
Table 147. UART Modem Control Register (MCR - address
Table 148. Modem status interrupt generation . . . . . . . . 145
Table 149. UART Line Status Register (LSR - address
Table 150: UART Modem Status Register (MSR - address
Table 151. UART Scratch Pad Register (SCR - address
Table 152. Auto-baud Control Register (ACR - address
Table 153. UART Fractional Divider Register (FDR - address
address 0x5000 0028 (GPIO0), 0x5001 0028
(GPIO1), 0x5002 0028 (GPIO2)) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
0x5000 002C (GPIO0), 0x5001 002C (GPIO1),
0x5002 002C (GPIO2)) bit description. . . . . . 134
0x5000 0030, 0x5001 0030 (GPIO1), 0x5002
0030 (GPIO2)) bit description . . . . . . . . . . . 135
address 0x5000 0034 (GPIO0), 0x5001 0034
(GPIO1), 0x5002 0034 (GPIO2)) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
address 0x5000 0038 (GPIO0), 0x5001 0038
(GPIO1), 0x5002 0038 (GPIO2)) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
003C, 0x5001 003C (GPIO1), 0x5002 003C
(GPIO2)) bit description . . . . . . . . . . . . . . . . 135
0x4000 8000) . . . . . . . . . . . . . . . . . . . . . . . . . 137
0x4000 8000 when DLAB = 0, Read Only) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
address 0x4000 8000 when DLAB = 0, Write
Only) bit description . . . . . . . . . . . . . . . . . . . . 138
0x4000 8000 when DLAB = 1) bit description 139
address 0x4000 8004 when DLAB = 1) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
0x4000 8004 when DLAB = 0) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . 139
address 0x4004 8008, Read Only) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . 140
0x4000 8008, Write Only) bit description . . . . 142
0x4000 800C) bit description . . . . . . . . . . . . 143
0x4000 8010) bit description . . . . . . . . . . . . . 144
0x4000 8014, Read Only) bit description . . . 146
0x4000 8018) bit description . . . . . . . . . . . . . 148
0x4000 801C) bit description . . . . . . . . . . . . . 148
0x4000 8020) bit description . . . . . . . . . . . . . 149
Chapter 26: Supplementary information
UM10441
© NXP B.V. 2011. All rights reserved.
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