OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 137

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
9.5 Register description
Table 137. Register overview: UART0 (base address: 0x4000 8000)
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UM10441
User manual
Name
RBR
THR
DLL
DLM
IER
IIR
FCR
LCR
MCR
LSR
MSR
SCR
ACR
-
FDR
-
TER
-
RS485CTRL
ADRMATCH
RS485DLY
FIFOLVL
Reset value reflects the data stored in used bits only. It does not include reserved bits content.
R/W
RO
R/W
RO
Access Address
RO
WO
R/W
R/W
WO
R/W
R/W
RO
RO
R/W
R/W
-
R/W
-
R/W
-
R/W
R/W
The UART contains registers organized as shown in
Bit (DLAB) is contained in LCR[7] and enables access to the Divisor Latches.
offset
0x000
0x000
0x000
0x004
0x004
0x008
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
0x034 -
0x048
0x04C
0x050
0x054
0x058
Description
Receiver Buffer Register. Contains the next received character to be read.
(DLAB=0)
Transmit Holding Register. The next character to be transmitted is written
here. (DLAB=0)
Divisor Latch LSB. Least significant byte of the baud rate divisor value.
The full divisor is used to generate a baud rate from the fractional rate
divider. (DLAB = 1)
Divisor Latch MSB. Most significant byte of the baud rate divisor value.
The full divisor is used to generate a baud rate from the fractional rate
divider. (DLAB = 1)
Interrupt Enable Register. Contains individual interrupt enable bits for the
7 potential UART interrupts. (DLAB=0)
Interrupt ID Register. Identifies which interrupt(s) are pending.
FIFO Control Register. Controls UART FIFO usage and modes.
Line Control Register. Contains controls for frame formatting and break
generation.
Modem control register
Line Status Register. Contains flags for transmit and receive status,
including line errors.
Modem status register
Scratch Pad Register. Eight-bit temporary storage for software.
Auto-baud Control Register. Contains controls for the auto-baud feature.
Reserved
Fractional Divider Register. Generates a clock input for the baud rate
divider.
Reserved
Transmit Enable Register. Turns off UART transmitter for use with
software flow control.
Reserved
RS-485/EIA-485 Control. Contains controls to configure various aspects
of RS-485/EIA-485 modes.
RS-485/EIA-485 address match. Contains the address match value for
RS-485/EIA-485 mode.
RS-485/EIA-485 direction control delay.
FIFO Level register. Provides the current fill levels of the transmit and
receive FIFOs.
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 March 2011
Chapter 9: LPC122x UART0 with modem control
Table
137. The Divisor Latch Access
UM10441
© NXP B.V. 2011. All rights reserved.
0x00
0x00
0x00
0x00
0x60
0x00
0x00
0x00
-
0x10
-
0x80
-
0x00
0x00
0x00
0x00
Reset
value
NA
NA
0x01
0x01
0x00
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