OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 257

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
Table 235. Register overview: 32-bit counter/timer 1 CT32B1 (base address 0x4001 C000)
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UM10441
User manual
Name
PR
PC
MCR
MR0
MR1
MR2
MR3
CCR
CR0
CR1
CR2
CR3
EMR
-
CTCR
PWMC
Reset value reflects the data stored in used bits only. It does not include reserved bits content.
14.7.1 Interrupt Register
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
R/W
-
R/W
R/W
The Interrupt Register consists of four bits for the match interrupts and four bits for the
capture interrupts. If an interrupt is generated then the corresponding bit in the IR will be
HIGH. Otherwise, the bit will be LOW. Writing a logic one to the corresponding IR bit will
reset the interrupt. Writing a zero has no effect. Clearing an interrupt for timer match also
clears any corresponding DMA request.
offset
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
0x034
0x038
0x03C
0x040 -
0x06C
0x070
0x074
Address
Description
Prescale Register. When the Prescale Counter (below) is equal to this
value, the next clock increments the TC and clears the PC.
Prescale Counter. The 32-bit PC is a counter which is incremented to
the value stored in PR. When the value in PR is reached, the TC is
incremented and the PC is cleared. The PC is observable and
controllable through the bus interface.
Match Control Register. The MCR is used to control if an interrupt is
generated and if the TC is reset when a Match occurs.
Match Register 0. MR0 can be enabled through the MCR to reset the
TC, stop both the TC and PC, and/or generate an interrupt every time
MR0 matches the TC.
Match Register 1. See MR0 description.
Match Register 2. See MR0 description.
Match Register 3. See MR0 description.
Capture Control Register. The CCR controls which edges of the capture
inputs are used to load the Capture Registers and whether or not an
interrupt is generated when a capture takes place.
Capture Register 0. CR0 is loaded with the value of TC when there is an
event on the CT32B1_CAP0 input.
Capture Register 1. CR1 is loaded with the value of TC when there is an
event on the CT32B1_CAP1 input.
Capture Register 2. CR2 is loaded with the value of TC when there is an
event on the CT32B1_CAP2 input.
Capture Register 3. CR3 is loaded with the value of TC when there is an
event on the CT32B1_CAP3 input.
External Match Register. The EMR controls the match function and the
external match pins CT32Bn_MAT[3:0].
reserved
Count Control Register. The CTCR selects between Timer and Counter
mode, and in Counter mode selects the signal and edge(s) for counting.
PWM Control Register. The PWMCON enables PWM mode for the
external match pins CT32Bn_MAT[3:0].
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 March 2011
Chapter 14: LPC122x 32-bit Counter/timer 0/1 (CT32B0/1)
…continued
UM10441
© NXP B.V. 2011. All rights reserved.
Reset
value
0
0
0
0
0
0
0
0
0
0
0
0
0
-
0
0
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