OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 167

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
10.5.6.1.1 UART receiver DMA
10.5.6.1.2 UART transmitter DMA
10.5.6.1 DMA operation
10.5.7 UART Line Control Register
Table 169. UART FIFO Control Register (FCR - address 0x4000 C008, Write Only) bit
The user can optionally operate the UART transmit and/or receive using the micro DMA.
The DMA mode is determined by the DMA Mode Select bit in the FCR register. This bit
only has an effect when the FIFOs are enabled via the FIFO Enable bit in the FCR
register.
In DMA mode, the receiver DMA request is asserted when the receiver FIFO level is equal
to or greater than trigger level, or if a character time-out occurs. See the description of the
RX Trigger Level above. The receiver DMA request is cleared by the DMA controller.
In DMA mode, the transmitter DMA request is asserted when the transmitter FIFO
transitions to not full. The transmitter DMA request is cleared by the DMA controller.
The LCR determines the format of the data character that is to be transmitted or received.
Table 170. UART Line Control Register (LCR - address 0x4000 C00C) bit description
Bit
7:6
31:8 -
Bit
1:0
2
3
Symbol Value Description
WLS
SBS
PE
Symbol
RXTL
description
0x0
0x1
0x2
0x3
0
1
0
1
All information provided in this document is subject to legal disclaimers.
Value Description
0x0
0x1
0x2
0x3
-
Word Length Select
5-bit character length.
6-bit character length.
7-bit character length.
8-bit character length.
Stop Bit Select
1 stop bit.
2 stop bits (1.5 if LCR[1:0]=00).
Parity Enable
Disable parity generation and checking.
Enable parity generation and checking.
RX Trigger Level. These two bits determine how many receiver
UART FIFO characters must be written before an interrupt is
activated.
Trigger level 0 (1 character or 0x01).
Trigger level 1 (4 characters or 0x04).
Trigger level 2 (8 characters or 0x08).
Trigger level 3 (14 characters or 0x0E).
Reserved
Rev. 1.1 — 10 March 2011
Chapter 10: LPC122x UART1
UM10441
© NXP B.V. 2011. All rights reserved.
167 of 442
Reset
value
0
-
Reset
value
0
0
0