OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 335

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
21.6.14 Channel primary-alternate clear register
21.6.15 Channel priority set register
This register is a write-only register and configures a DMA channel to use the primary
data structure. Writing to a bit where a DMA channel is not implemented has no effect.
Remark: The controller toggles the value of the CHNL_PRI_ALT_CLR[c] bit after it
completes one of the following:
Table 334. Channel primary-alternate clear register (CHNL_PRI_ALT_CLR, address 0x4004
This register is read/write register and configures a DMA c (c = 0 to 20) channel to use the
high priority level. Reading the register returns the status of the channel priority mask.
Writing to a bit where a DMA channel is not implemented has no effect.
Bit
20:0
31:21
•
•
•
the four transfers that the primary data structure specifies for a memory scatter-gather
or peripheral scatter-gather DMA cycle.
all the transfers that the primary data structure specifies for a ping-pong DMA cycle.
all the transfers that the alternate data structure specifies for the following DMA cycle
types:
– ping-pong.
– memory scatter-gather. For details, see the ARM micro DMA (PL230)
– peripheral scatter-gather. For details, see the ARM micro DMA (PL230)
documentation.
documentation.
Symbol
CHNL_PRI_ALT_
CLR
-
C034) bit description
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 March 2011
Chapter 21: LPC122x General purpose micro DMA controller
Description
Set the appropriate bit to select the primary data structure for
the corresponding DMA channel c.
Write as:
Bit [c] = 0: No effect. Use the CHNL_PRI_ALT_SET Register
to select the alternate data structure.
Bit [c] = 1: Selects the primary data structure for channel c.
Reserved.
UM10441
© NXP B.V. 2011. All rights reserved.
335 of 442
Reset
value
-
-