OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 146

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
Fig 6.
UART TX
CTS pin
Auto-CTS Functional Timing
9.5.9 UART Line Status Register
start
bits0..7
The auto-CTS function reduces interrupts to the host system. When flow control is
enabled, a CTS state change does not trigger host interrupts because the device
automatically controls its own transmitter. Without Auto-CTS, the transmitter sends any
data present in the transmit FIFO and a receiver overrun error can result.
illustrates the Auto-CTS functional timing.
While starting transmission of the initial character the CTS signal is asserted.
Transmission will stall as soon as the pending transmission has completed. The UART will
continue transmitting a 1 bit as long as CTS is deasserted (high). As soon as CTS gets
deasserted transmission resumes and a start bit is sent followed by the data bits of the
next character.
The LSR is a Read Only register that provides status information on the UART TX and RX
blocks.
Table 149. UART Line Status Register (LSR - address 0x4000 8014, Read Only) bit
Bit
0
1
2
Symbol
RDR
OE
PE
stop
description
All information provided in this document is subject to legal disclaimers.
Value Description
0
1
0
1
0
1
Rev. 1.1 — 10 March 2011
Receiver Data Ready:LSR[0] is set when the RBR holds an
unread character and is cleared when the UART RBR FIFO is
empty.
RBR is empty.
RBR contains valid data.
Overrun Error. The overrun error condition is set as soon as it
occurs. A LSR read clears LSR[1]. LSR[1] is set when UART
RSR has a new character assembled and the UART RBR
FIFO is full. In this case, the UART RBR FIFO will not be
overwritten and the character in the UART RSR will be lost.
Overrun error status is inactive.
Overrun error status is active.
Parity Error. When the parity bit of a received character is in
the wrong state, a parity error occurs. A LSR read clears
LSR[2]. Time of parity error detection is dependent on FCR[0].
Note: A parity error is associated with the character at the top
of the UART RBR FIFO.
Parity error status is inactive.
Parity error status is active.
start
bits0..7
Chapter 9: LPC122x UART0 with modem control
stop
start
UM10441
© NXP B.V. 2011. All rights reserved.
Figure 6
bits0..7
146 of 442
stop
Reset
Value
0
0
0