OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 214

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
11.10.7.4 I
11.10.7.5 Bus error
An I
the bus. If the SCL line is obstructed (pulled LOW) by a device on the bus, no further serial
transfer is possible, and the problem must be resolved by the device that is pulling the
SCL bus line LOW.
Typically, the SDA line may be obstructed by another device on the bus that has become
out of synchronization with the current bus master by either missing a clock, or by sensing
a noise pulse as a clock. In this case, the problem can be solved by transmitting additional
clock pulses on the SCL line
time-out timer to detect an obstructed bus, but this can be implemented using another
timer in the system. When detected, software can force clocks (up to 9 may be required)
on SCL until SDA is released by the offending device. At that point, the slave may still be
out of synchronization, so a START should be generated to insure that all I
are synchronized.
A bus error occurs when a START or STOP condition is detected at an illegal position in
the format frame. Examples of illegal positions are during the serial transfer of an address
byte, a data bit, or an acknowledge bit.
2
Fig 27. Forced access to a busy I
Fig 28. Recovering from a bus obstruction caused by a LOW level on SDA
C-bus obstructed by a LOW level on SCL or SDA
2
C-bus hang-up can occur if either the SDA or SCL line is held LOW by any device on
(1) Unsuccessful attempt to send a START condition.
(2) SDA line is released.
(3) Successful attempt to send a START condition. State 08H is entered.
STO flag
SDA line
STA flag
SCL line
STA flag
SDA line
SCL line
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 March 2011
(1)
Figure
time limit
2
C-bus
28. The I
(1)
2
C interface does not include a dedicated
Chapter 11: LPC122x I2C-bus controller
(2)
condition
(3)
start
condition
start
UM10441
© NXP B.V. 2011. All rights reserved.
2
C peripherals
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