OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 392

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
25.4.5.1.2 Operation
25.4.5.1.3 Restrictions
ADD{S} {Rd,} Rn, <Rm|#imm>
RSBS {Rd,} Rn, Rm, #0
SBCS {Rd,} Rn, Rm
SUB{S} {Rd,} Rn,
<Rm|#imm>
Where:
When the optional Rd register specifier is omitted, it is assumed to take the same value as
Rn, for example ADDS R1,R2 is identical to ADDS R1,R1,R2.
The ADCS instruction adds the value in Rn to the value in Rm, adding a further one if the
carry flag is set, places the result in the register specified by Rd and updates the N, Z, C,
and V flags.
The ADD instruction adds the value in Rn to the value in Rm or an immediate value
specified by imm and places the result in the register specified by Rd.
The ADDS instruction performs the same operation as ADD and also updates the N, Z, C
and V flags.
The RSBS instruction subtracts the value in Rn from zero, producing the arithmetic
negative of the value, and places the result in the register specified by Rd and updates the
N, Z, C and V flags.
The SBCS instruction subtracts the value of Rm from the value in Rn, deducts a further
one if the carry flag is set. It places the result in the register specified by Rd and updates
the N, Z, C and V flags.
The SUB instruction subtracts the value in Rm or the immediate specified by imm. It
places the result in the register specified by Rd.
The SUBS instruction performs the same operation as SUB and also updates the N, Z, C
and V flags.
Use ADC and SBC to synthesize multiword arithmetic, see
See also
Table 369
be used with each instruction.
S causes an ADD or SUB instruction to update flags
Rd specifies the result register
Rn specifies the first source register
Rm specifies the second source register
imm specifies a constant immediate value.
Section
lists the legal combinations of register specifiers and immediate values that can
All information provided in this document is subject to legal disclaimers.
25–25.4.4.1.
Rev. 1.1 — 10 March 2011
Chapter 25: LPC122x Appendix ARM Cortex-M0
Section
25.4.5.1.4.
UM10441
© NXP B.V. 2011. All rights reserved.
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