OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 48

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
4.7.3.1 Power configuration in Deep-sleep mode
4.7.3.2 Programming Deep-sleep mode
Deep-sleep mode eliminates all power used by the flash, analog peripherals and all
dynamic power used by the processor itself, memory systems and their related
controllers, and internal buses. The processor state and registers, peripheral registers,
and internal SRAM values are maintained, and the logic levels of the pins remain static.
Power consumption in Deep-sleep mode is determined by the Deep-sleep power
configuration setting in the PDSLEEPCFG
The following steps must be performed to enter Deep-sleep mode:
1. The DPDEN bit in the PCON register must be set to zero
2. Select the power configuration in Deep-sleep mode in the PDSLEEPCFG
3. Select the power configuration after wake-up in the PDAWAKECFG
4. Configure the start logic:
5. In the SYSAHBCLKCTRL register
6. Write one to the SLEEPDEEP bit in the ARM Cortex-M0 SCR register
7. Use the ARM WFI instruction.
•
•
•
•
Except for the RTC oscillator, the only clock source available in Deep-sleep mode is
the watchdog oscillator. The watchdog oscillator can be left running in Deep-sleep
mode if required for peripheral-controlled wake-up (see
sources (the IRC and system oscillator) and the system PLL are shut down. The
watchdog oscillator analog output frequency must be set to the lowest value of its
analog clock output (bits FREQSEL in the WDTOSCCTRL = 0001, see
The BOD circuit can be left running in Deep-sleep mode if required by the application.
If the watchdog oscillator is running in Deep-sleep mode, only the watchdog timer
should be enabled in SYSAHBCLKCTRL register to minimize power consumption.
The RTC and the RTC oscillator can be left running in Deep-sleep mode.
register.
a. For peripheral controlled wake-up, ensure that the watchdog oscillator is powered
b. Without peripheral controlled wake-up and if the watchdog oscillator is shut down,
register.
– If an external pin is used for wake-up, enable and clear the wake-up pin in the start
– If the RTC is used, enable and clear bit 18 in the start logic 1 registers
WDT if needed.
in the PDRUNCFG register and switch the clock source to WD oscillator in the
MAINCLKSEL register
ensure that the IRC is powered in the PDRUNCFG register and switch the clock
source to IRC in the MAINCLKSEL register
system clock is shut down glitch-free.
logic 0 registers
NVIC.
Table
45), and enable the RTC interrupt in the NVIC.
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 March 2011
(Table 37
(Table
to
Table
18).
(Table
Chapter 4: LPC122x System control (SYSCON)
40), and enable the start logic interrupt in the
(Table
21), disable all peripherals except RTC or
48) register:
(Table
18). This ensures that the
Section
(Table
4.8.3). All other clock
56).
UM10441
© NXP B.V. 2011. All rights reserved.
(Table
(Table
Table
(Table 42
(Table
49)
386).
13).
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