OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 18

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
4.5.5 System oscillator control register
4.5.6 Watchdog oscillator control register
This register configures the frequency range for the system oscillator.
Table 12.
This register configures the watchdog oscillator. The oscillator consists of an analog and a
digital part. The analog part contains the oscillator function and generates an analog clock
(Fclkana). With the digital part, the analog output clock (Fclkana) can be divided to the
required output clock frequency wdt_osc_clk. The analog output frequency (Fclkana) can
be adjusted with the FREQSEL bits between 500 kHz and 3.4 MHz. With the digital part
Fclkana will be divided (divider ratios = 2, 4,...,64) to wdt_osc_clk using the DIVSEL bits.
The output clock frequency of the watchdog oscillator can be calculated as
wdt_osc_clk =
Remark: Any setting of the FREQSEL bits will yield a Fclkana value within ± 40% of the
listed frequency value. The watchdog oscillator is the clock source with the lowest power
consumption. If accurate timing is required, use the IRC or system clock.
Remark: The frequency of the watchdog oscillator is undefined after reset. The watchdog
oscillator frequency must be programmed by writing to the WDTOSCCTRL register before
using the watchdog oscillator.
Table 13.
Bit
0
1
31:2
Bit
4:0
Symbol
BYPASS
FREQRANGE
-
Symbol
DIVSEL
System oscillator control register (SYSOSCCTRL, address 0x4004 8020) bit
description
Watchdog oscillator control register (WDTOSCCTRL, address 0x4004 8024) bit
description
Fclkana
All information provided in this document is subject to legal disclaimers.
Value
?
(2 × (1 + DIVSEL))
Rev. 1.1 — 10 March 2011
Description
Select divider for Fclkana.
wdt_osc_clk = Fclkana/ (2 × (1 + DIVSEL))
00000: 2 × (1 + DIVSEL) = 2
00001: 2 × (1 + DIVSEL) = 4
to
11111: 2 × (1 + DIVSEL) = 64
Value
0
1
0
1
-
Description
Bypass system oscillator
Oscillator is not bypassed.
Bypass enabled. PLL input (sys_osc_clk) is fed
directly from the XTALIN and XTALOUT pins.
Determines frequency range for Low-power
oscillator.
1 - 20 MHz frequency range.
15 - 25 MHz frequency range
Reserved
= 7.8 kHz to 1.7 MHz (nominal values).
Chapter 4: LPC122x System control (SYSCON)
UM10441
© NXP B.V. 2011. All rights reserved.
18 of 442
Reset
value
0
0
0x00
Reset
value
0