OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 404

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
25.4.7.3.2 Operation
25.4.7.3.3 Restrictions
25.4.7.3.4 Condition flags
25.4.7.3.5 Examples
25.4.7.4.1 Syntax
25.4.7.4.2 Operation
25.4.7.4.3 Restrictions
25.4.7.4.4 Condition flags
25.4.7.4.5 Examples
25.4.7.5.1 Syntax
25.4.7.5.2 Operation
25.4.7.4 DSB
25.4.7.5 ISB
DMB acts as a data memory barrier. It ensures that all explicit memory accesses that
appear in program order before the DMB instruction are observed before any explicit
memory accesses that appear in program order after the DMB instruction. DMB does not
affect the ordering of instructions that do not access memory.
There are no restrictions.
This instruction does not change the flags.
Data Synchronization Barrier.
DSB
DSB acts as a special data synchronization memory barrier. Instructions that come after
the DSB, in program order, do not execute until the DSB instruction completes. The DSB
instruction completes when all explicit memory accesses before it complete.
There are no restrictions.
This instruction does not change the flags.
Instruction Synchronization Barrier.
ISB
ISB acts as an instruction synchronization barrier. It flushes the pipeline of the processor,
so that all instructions following the ISB are fetched from cache or memory again, after the
ISB instruction has been completed.
DMB ; Data Memory Barrier
DSB ; Data Synchronisation Barrier
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 March 2011
Chapter 25: LPC122x Appendix ARM Cortex-M0
UM10441
© NXP B.V. 2011. All rights reserved.
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