OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 247

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
Table 229. External Match Register (EMR, address 0x4001 003C (CT16B0) and 0x4001 403C (CT16B1)) bit
UM10441
User manual
Bit
0
1
2
3
5:4 EMC0
Symbol
EM0
EM1
EM2
EM3
description
13.7.10 External Match Register
Value Description
0x0
0x1
0x2
0x3
Table 228: Capture registers (CR0 to 3, addresses 0x4001 002C to 38 (CT16B0) and
The External Match Register provides both control and status of the external match pins
CT16Bn_MAT[1:0].
Match events for Match 0 and Match 1 in each timer can cause a DMA request.
If the match outputs are configured as PWM output, the function of the external match
registers is determined by the PWM rules
controlled PWM outputs” on page
Bit
15:0
31:16
External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0,
whether or not this output is connected to its pin. When a match occurs between the TC
and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4]
control the functionality of this output. This bit is driven to the
CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON
registers (0 = LOW, 1 = HIGH).
External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1,
whether or not this output is connected to its pin. When a match occurs between the TC
and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6]
control the functionality of this output. This bit is driven to the
CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON
registers (0 = LOW, 1 = HIGH).
External Match 2. This bit reflects the state of match channel 2. When a match occurs
between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits
EMR[9:8] control the functionality of this output.
External Match 3. This bit reflects the state of output of match channel 3. When a match
occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do
nothing. Bits EMR[11:10] control the functionality of this output.
External Match Control 0. Determines the functionality of External Match 0.
shows the encoding of these bits.
Do Nothing.
Clear the corresponding External Match bit/output to 0 (CT16Bi_MAT0 pin is LOW if
pinned out).
Set the corresponding External Match bit/output to 1 (CT16Bi_MAT0 pin is HIGH if pinned
out).
Toggle the corresponding External Match bit/output.
Symbol
CAP
-
0x4001 402C to 38 (CT16B1)) bit description
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 March 2011
Description
Timer counter capture value.
Reserved.
Chapter 13: LPC122x 16-bit Counter/timer 0/1 (CT16B0/1)
251).
(Section 13.7.13 “Rules for single edge
Table 230
UM10441
© NXP B.V. 2011. All rights reserved.
247 of 442
Reset
value
0
-
Reset
value
0
0
0
0
00