OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 265

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
Bits 7:4 of this register are also used to enable and configure the capture-clears-timer
feature. This feature allows for a designated edge on a particular CAP input to reset the
timer to all zeros. Using this mechanism to clear the timer on the leading edge of an input
pulse and performing a capture on the trailing edge, permits direct pulse-width
measurement using a single capture input without the need to perform a subtraction
operation in software.
Table 247: Count Control Register (CTCR, address 0x4001 8070 (CT32B0) and 0x4001 C070
Bit
1:0
3:2
4
Symbol
CTM
CIS
ENCC
(CT32B1)) bit description
All information provided in this document is subject to legal disclaimers.
Value
0x0
0x1
0x2
0x3
0x0
0x1
0x2
0x3
Rev. 1.1 — 10 March 2011
Description
Counter/Timer Mode. This field selects which rising PCLK
edges can increment Timer’s Prescale Counter (PC), or clear
PC and increment Timer Counter (TC).
Remark: If Counter mode is selected in the CTCR, bits 2:0 in
the Capture Control Register (CCR) must be programmed as
000.
Timer Mode: every rising PCLK edge
Counter Mode: TC is incremented on rising edges on the
CAP input selected by bits 3:2.
Counter Mode: TC is incremented on falling edges on the
CAP input selected by bits 3:2.
Counter Mode: TC is incremented on both edges on the CAP
input selected by bits 3:2.
Count Input Select. In counter mode (when bits 1:0 in this
register are not 00), these bits select which CAP pin or
comparator output is sampled for clocking.
Remark: If Counter mode is selected in the CTCR, the 3 bits
for that input in the Capture Control Register (CCR) must be
programmed as 000.
CT32Bn_CAP0
CT32Bn_CAP1
CT32Bn_CAP2
CT32Bn_CAP3
Setting this bit to 1 enables clearing of the timer and the
prescaler when the capture-edge event specified in bits 7:5
occurs.
Chapter 14: LPC122x 32-bit Counter/timer 0/1 (CT32B0/1)
UM10441
© NXP B.V. 2011. All rights reserved.
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Reset
value
00
00
0