OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 343

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
21.7.5.1 Source data end pointer
21.7.5.2 Destination data end pointer
The DMA channel control data structure must be programmed in the LPC122x’s SRAM
memory. The data structure must be aligned on a 256 byte boundary to create a
contiguous area for 21 channel control data structures and 21 alternate channel control
data structures. The base address of the primary channel control data structure in SRAM
must be between 0x1000 0000 and 0x1000 1F00 in increments of 0x100 (see
The pointer to the base address of the channel control data structure is programmed in
the CTRL_BASE_PTR register
Remark: The user memory (SRAM) is not accessed by the DMA controller unless the
channel is enabled and a transfer is started for this channel.
The src_data_end_ptr memory location contains a pointer to the end address of the
source data.
Before the controller can perform a DMA transfer, this memory location must be
programmed with the end address of the source data. The controller reads this memory
location when it starts a 2
counts down from the end address, and before each arbitration, the channel control data
structure is updated with the number of remaining transfers.
Remark: The controller does not write to this memory location.
Table 343. src_data_end_ptr bit assignments
The dst_data_end_ptr memory location contains a pointer to the end address of the
destination data.
Before the controller can perform a DMA transfer, this memory location must be
programmed with the end address of the destination data. The controller reads this
memory location when it starts a 2
control data structure is updated with the number of remaining transfers.
Bit
31:0
Fig 57. Memory map for the micro DMA channel control data structure (8 channels)
Name
src_data_end_ptr
alternate channel 20
All information provided in this document is subject to legal disclaimers.
alternate channel 1
alternate channel 0
primary channel 20
primary channel 1
primary channel 0
Rev. 1.1 — 10 March 2011
Chapter 21: LPC122x General purpose micro DMA controller
R
DMA transfer. During a DMA transfer cycle, the controller
Description
Pointer to the end address of the source data
(Table
R
0x2A0
0x2B0
0x170
0x160
0x150
0x140
0x020
0x010
0x000
DMA transfer, and before each arbitration the channel
323).
destination end pointer
channel control data
source end pointer
unused
UM10441
© NXP B.V. 2011. All rights reserved.
0x00C
0x008
0x004
0x000
Figure
343 of 442
57).