OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 184

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
When I2EN is “0”, the SDA and SCL input signals are ignored, the I
addressed” slave state, and the STO bit is forced to “0”.
I2EN should not be used to temporarily release the I
I
STA is the START flag. Setting this bit causes the I
transmit a START condition or transmit a Repeated START condition if it is already in
master mode.
When STA is 1 and the I
checks the bus and generates a START condition if the bus is free. If the bus is not free, it
waits for a STOP condition (which will free the bus) and generates a START condition
after a delay of a half clock period of the internal clock generator. If the I
already in master mode and data has been transmitted or received, it transmits a
Repeated START condition. STA may be set at any time, including when the I
is in an addressed slave mode.
STA can be cleared by writing 1 to the STAC bit in the I2CONCLR register. When STA is
0, no START condition or Repeated START condition will be generated.
If STA and STO are both set, then a STOP condition is transmitted on the I
interface is in master mode, and transmits a START condition thereafter. If the I
interface is in slave mode, an internal STOP condition is generated, but is not transmitted
on the bus.
STO is the STOP flag. Setting this bit causes the I
condition in master mode, or recover from an error condition in slave mode. When STO is
1 in master mode, a STOP condition is transmitted on the I
the STOP condition, STO is cleared automatically.
In slave mode, setting this bit can recover from an error condition. In this case, no STOP
condition is transmitted to the bus. The hardware behaves as if a STOP condition has
been received and it switches to “not addressed” slave receiver mode. The STO flag is
cleared by hardware automatically.
SI is the I
state F8 does not set SI since there is nothing for an interrupt service routine to do in that
case.
While SI is set, the low period of the serial clock on the SCL line is stretched, and the
serial transfer is suspended. When SCL is HIGH, it is unaffected by the state of the SI flag.
SI must be reset by software, by writing a 1 to the SIC bit in I2CONCLR register.
AA is the Assert Acknowledge Flag. When set to 1, an acknowledge (low level to SDA)
will be returned during the acknowledge clock pulse on the SCL line on the following
situations:
2
1. The address in the Slave Address Register has been received.
2. The General Call address has been received while the General Call bit (GC) in I2ADR
3. A data byte has been received while the I
4. A data byte has been received while the I
C-bus status is lost. The AA flag should be used instead.
is set.
2
C Interrupt Flag. This bit is set when the I
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 March 2011
2
C interface is not already in master mode, it enters master mode,
2
2
C is in the master receiver mode.
C is in the addressed slave receiver mode
Chapter 11: LPC122x I2C-bus controller
2
2
C interface to transmit a STOP
C interface to enter master mode and
2
2
C-bus since, when I2EN is reset, the
C state changes. However, entering
2
C-bus. When the bus detects
2
C block is in the “not
UM10441
© NXP B.V. 2011. All rights reserved.
2
C interface is
2
C-bus if it the
2
C interface
2
C
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