OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 357

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
25.2.1 System-level interface
25.2.2 Integrated configurable debug
25.2.3 Cortex-M0 processor features summary
25.2.4 Cortex-M0 core peripherals
The Cortex-M0 processor closely integrates a configurable Nested Vectored Interrupt
Controller (NVIC), to deliver industry-leading interrupt performance. The NVIC:
The tight integration of the processor core and NVIC provides fast execution of interrupt
service routines (ISRs), dramatically reducing the interrupt latency. This is achieved
through the hardware stacking of registers, and the ability to abandon and restart
load-multiple and store-multiple operations. Interrupt handlers do not require any
assembler wrapper code, removing any code overhead from the ISRs. Tail-chaining
optimization also significantly reduces the overhead when switching from one ISR to
another.
To optimize low-power designs, the NVIC integrates with the sleep modes, that include a
Deep-sleep function that enables the entire device to be rapidly powered down.
The Cortex-M0 processor provides a single system-level interface using AMBA
technology to provide high speed, low latency memory accesses.
The Cortex-M0 processor implements a complete hardware debug solution, with
extensive hardware breakpoint and watchpoint options. This provides high system
visibility of the processor, memory and peripherals through a 2-pin Serial Wire Debug
(SWD) port that is ideal for microcontrollers and other small package devices.
These are:
NVIC — The NVIC is an embedded interrupt controller that supports low latency interrupt
processing.
System Control Block — The System Control Block (SCB) is the programmers model
interface to the processor. It provides system implementation information and system
control, including configuration, control, and reporting of system exceptions.
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includes a non-maskable interrupt (NMI).
provides zero jitter interrupt option.
provides four interrupt priority levels.
high code density with 32-bit performance
tools and binary upwards compatible with Cortex-M processor family
integrated ultra low-power sleep modes
efficient code execution permits slower processor clock or increases sleep mode time
single-cycle 32-bit hardware multiplier
zero jitter interrupt handling
extensive debug capabilities.
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 March 2011
Chapter 25: LPC122x Appendix ARM Cortex-M0
UM10441
© NXP B.V. 2011. All rights reserved.
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