OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 260

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
Table 241: Match Control Register (MCR, address 0x4001 8014 (CT32B0) and 0x4001 C014 (CT32B1)) bit description
UM10441
User manual
Bit
5
6
7
8
9
10
11
31:12
Symbol Value Description
MR1S
MR2I
MR2R
MR2S
MR3I
MR3R
MR3S
-
14.7.7 Match Registers
1
0
1
0
1
0
1
0
1
0
1
0
1
0
The Match register values are continuously compared to the Timer Counter value. When
the two values are equal, actions can be triggered automatically. The action possibilities
are to generate an interrupt, reset the Timer Counter, or stop the timer. Actions are
controlled by the settings in the MCR register.
Table 242: Match registers (MR0 to 3, addresses 0x4001 8018 to 24 (CT32B0) and
Bit
31:0
Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches
the TC.
Enabled
Disabled
Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.
Enabled
Disabled
Reset on MR2: the TC will be reset if MR2 matches it.
Enabled
Disabled
Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches
the TC.
Enabled
Disabled
Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.
Enabled
Disabled
Reset on MR3: the TC will be reset if MR3 matches it.
Enabled
Disabled
Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches
the TC.
Enabled
Disabled
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Symbol
MATCH
0x4001 C018 to 24 (CT32B1)) bit description
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 March 2011
Description
Timer counter match value.
Chapter 14: LPC122x 32-bit Counter/timer 0/1 (CT32B0/1)
UM10441
© NXP B.V. 2011. All rights reserved.
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Reset
value
0
0
0
0
0
0
0
NA
Reset
value
0