OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 246

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
Table 227. Capture Control Register (CCR, address 0x4001 0028 (CT16B0) and 0x4001 4028 (CT16B1)) bit
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Bit
4
5
6
7
8
9
10
11
31:12 -
Symbol
CAP1FE
CAP1I
CAP2RE
CAP2FE
CAP2I
CAP3RE
CAP3FE
CAP3I
description
13.7.9 Capture Registers
Value Description
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
-
Each Capture register is associated with a device pin and may be loaded with the
counter/timer value when a specified event occurs on that pin. The settings in the Capture
Control Register register determine whether the capture function is enabled, and whether
a capture event happens on the rising edge of the associated pin, the falling edge, or on
both edges.
Capture on CT16Bn_CAP1 falling edge: a sequence of 1 then 0 on CT16Bn_CAP1 will
cause CR1 to be loaded with the contents of TC.
Enabled.
Disabled.
Interrupt on CT16Bn_CAP1 event: a CR1 load due to a CT16Bn_CAP1 event will
generate an interrupt.
Enabled.
Disabled.
Capture on comparator n level output - rising edge: a sequence of 0 then 1 on the
comparator n output will cause CR2 to be loaded with the contents of TC.
Enabled.
Disabled.
Capture on comparator n level output - falling edge: a sequence of 1 then 0 on
comparator n output will cause CR2 to be loaded with the contents of TC.
Enabled.
Disabled.
Interrupt on comparator n level output event: a CR2 load due to a comparator 0 event
Capture on comparator n edge output - rising edge: a sequence of 0 then 1 on the
will generate an interrupt.
Enabled.
Disabled.
comparator n output will cause CR3 to be loaded with the contents of TC.
Enabled.
Disabled.
Capture on comparator n edge output - falling edge: a sequence of 1 then 0 on
comparator n output will cause CR3 to be loaded with the contents of TC.
Enabled.
Disabled.
Interrupt on comparator n edge output event: a CR3 load due to a comparator n event
will generate an interrupt.
Enabled.
Disabled.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 March 2011
Chapter 13: LPC122x 16-bit Counter/timer 0/1 (CT16B0/1)
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Reset
value
0
0
0
0
0
0
0
0
NA