OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 329

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
21.6.2 DMA configuration register
Table 321. DMA status register (DMA_STATUS, address 0x4004 C000) bit description
This register is a write-only register and configures the micro DMA controller.
The CHNL_PROT_CTRLn bits (bits 6:5) configure the protection control for AHB access
to the channel control data structure and should be set to zero for normal operation of the
DMA controller.
Table 322. DMA configuration register (DMA_CFG, address 0x4004 C004) bit description
Bit
0
3:1
7:4
15:8
20:16
31:21
Bit
0
4:1
5
6
31:7
Symbol
MASTER_EN
-
CHNL_PROT_CTRL1
CHNL_PROT_CTRL2
-
Symbol
MASTER_EN
-
STATE
-
-
CHNLS
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 March 2011
Chapter 21: LPC122x General purpose micro DMA controller
Description
Enable status of the controller:
0 = controller disabled.
1 = controller enabled.
Reserved.
Current state of the control state machine. State can
be one of the following:
0000 = idle
0001 = reading channel controller data
0010 = reading source data end pointer
0011 = reading destination data end pointer
0100 = reading source data
0101 = writing destination data
0110 = waiting for DMA request to clear
0111 = writing channel controller data
1000 = stalled
1001 = done
1010 = peripheral scatter-gather transition
1011-1111 = undefined
Reserved.
The LPC122x micro DMA controller is configured for
21 channels. Reset value is number of channels − 1.
Reserved.
Value
0
1
0
1
0
1
Description
Enable for the controller:
Disables the controller.
Enables the controller.
Reserved. Write as zero.
Channel protection access control:
User access
Privileged access
Channel protection buffer control:
Non-bufferable
Bufferable
Reserved. Write as zero.
UM10441
© NXP B.V. 2011. All rights reserved.
Reset value
-
-
-
-
-
Reset
value
-
-
10100
-
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