OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 157

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
9.5.18.1 RS-485/EIA-485 Normal Multidrop Mode (NMM)
9.5.18.2 RS-485/EIA-485 Auto Address Detection (AAD) mode
9.5.18.3 RS-485/EIA-485 Auto Direction Control
9.5.18 RS-485/EIA-485 modes of operation
The RS-485/EIA-485 feature allows the UART to be configured as an addressable slave.
The addressable slave is one of multiple slaves controlled by a single master.
The UART master transmitter will identify an address character by setting the parity (9th)
bit to ‘1’. For data characters, the parity bit is set to ‘0’.
Each UART slave receiver can be assigned a unique address. The slave can be
programmed to either manually or automatically reject data following an address which is
not theirs.
Setting the RS485CTRL bit 0 enables this mode. In this mode, an address is detected
when a received byte causes the UART to set the parity error and generate an interrupt.
If the receiver is disabled (RS485CTRL bit 1 = ‘1’), any received data bytes will be ignored
and will not be stored in the RXFIFO. When an address byte is detected (parity bit = ‘1’) it
will be placed into the RXFIFO and an RX Data Ready Interrupt will be generated. The
processor can then read the address byte and decide whether or not to enable the
receiver to accept the following data.
While the receiver is enabled (RS485CTRL bit 1 =’0’), all received bytes will be accepted
and stored in the RXFIFO regardless of whether they are data or address. When an
address character is received a parity error interrupt will be generated and the processor
can decide whether or not to disable the receiver.
When both RS485CTRL register bits 0 (9-bit mode enable) and 2 (AAD mode enable) are
set, the UART is in auto address detect mode.
In this mode, the receiver will compare any address byte received (parity = ‘1’) to the 8-bit
value programmed into the RS485ADRMATCH register.
If the receiver is disabled (RS485CTRL bit 1 = ‘1’), any received byte will be discarded if it
is either a data byte OR an address byte which fails to match the RS485ADRMATCH
value.
When a matching address character is detected it will be pushed onto the RXFIFO along
with the parity bit, and the receiver will be automatically enabled (RS485CTRL bit 1 will be
cleared by hardware). The receiver will also generate n RX Data Ready Interrupt.
While the receiver is enabled (RS485CTRL bit 1 = ‘0’), all bytes received will be accepted
and stored in the RXFIFO until an address byte which does not match the
RS485ADRMATCH value is received. When this occurs, the receiver will be automatically
disabled in hardware (RS485CTRL bit 1 will be set), The received non-matching address
character will not be stored in the RXFIFO.
RS485/EIA-485 mode includes the option of allowing the transmitter to automatically
control the state of the DIR pin as a direction control output signal.
Setting RS485CTRL bit 4 = ‘1’ enables this feature.
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 March 2011
Chapter 9: LPC122x UART0 with modem control
UM10441
© NXP B.V. 2011. All rights reserved.
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