OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 136

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OM13008,598

Manufacturer Part Number
OM13008,598
Description
BOARD LPC XPRESSO LPC122X
Manufacturer
NXP Semiconductors
Series
LPCXpressor
Datasheets

Specifications of OM13008,598

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-6642
OM13008
9.1 How to read this chapter
9.2 Basic configuration
9.3 Features
9.4 Pin description
UM10441
User manual
UART0 is available on all LPC122x parts.
Clocks and power to the UART0 block are controlled by:
Remark: The UART0 pins must be configured in the corresponding IOCON registers
before the UART0 clocks are enabled.
The UART0_PCLK can be disabled in the UART0CLKDIV register (see
the UART block can be disabled through the System AHB clock control register bit 12
(see
Table 136. UART0 pin description
Pin
RXD0
TXD0
RTS0
DTR0
DSR0
CTS0
DCD0
RI0
1. the SYSAHBCLKCTRL register (see
2. the UART0_PCLK which is enabled in the UART0 clock divider register (see
UM10441
Chapter 9: LPC122x UART0 with modem control
Rev. 1.1 — 10 March 2011
Table
16-byte receive and transmit FIFOs.
Register locations conform to ‘550 industry standard.
Receiver FIFO trigger points at 1, 4, 8, and 14 byte.
Built-in baud rate generator.
UART allows for implementation of either software or hardware flow control.
RS-485/EIA-485 9-bit mode support with output enable.
Modem control.
Table
23). This clock is used by the UART baud rate generator.
Type
Input
Output Serial Output. Serial transmit data.
Output Request To Send. RS-485 direction control pin.
Output Data Terminal Ready.
Input
Input
Input
Input
21) for power savings.
All information provided in this document is subject to legal disclaimers.
Description
Serial Input. Serial receive data.
Data Set Ready.
Clear To Send.
Data Carrier Detect.
Ring Indicator.
Rev. 1.1 — 10 March 2011
Table
21).
© NXP B.V. 2011. All rights reserved.
Table
User manual
23) and the
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