OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 283

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
Table 265. Watchdog operating modes selection
UM10441
User manual
WDEN
0
1
1
WDRESET
X (0 or 1)
0
1
17.7.2 Watchdog Timer Constant register
17.7.3 Watchdog Feed register
The TC register determines the time-out value. Every time a feed sequence occurs, the
TC content is reloaded into the Watchdog timer. This is pre-loaded with the value 0x00
FFFF upon reset. Writing values below 0xFF will cause 0xFF to be loaded into the TC.
Thus the minimum time-out interval is T
If the WDPROTECT bit in MOD = 1, an attempt to change the value of TC before the
watchdog counter is below the values of WARNINT and WINDOW will cause a watchdog
reset and set the WDTOF flag.
Table 266. Watchdog Timer Constant register (TC - 0x4000 4004) bit description
Writing 0xAA followed by 0x55 to this register will reload the Watchdog timer with the
WDTC value. This operation will also start the Watchdog if it is enabled via the WDMOD
register. Setting the WDEN bit in the WDMOD register is not sufficient to enable the
Watchdog. A valid feed sequence must be completed after setting WDEN before the
Watchdog is capable of generating a reset. Until then, the Watchdog will ignore feed
errors. After writing 0xAA to WDFEED, access to any Watchdog register other than writing
0x55 to WDFEED causes an immediate reset/interrupt when the Watchdog is enabled,
and sets the WDTOF flag. The reset will be generated during the second PCLK following
an incorrect access to a Watchdog register during a feed sequence.
Interrupts should be disabled during the feed sequence. An abort condition will occur if an
interrupt happens during the feed sequence.
Table 267. Watchdog Feed register (FEED - 0x4000 4008) bit description
Mode of Operation
Debug/Operate without the Watchdog running.
Watchdog interrupt mode: the watchdog warning interrupt will be generated but watchdog reset will
not.
When this mode is selected, the watchdog counter reaching the value specified by WDWARNINT
will set the WDINT flag and the Watchdog interrupt request will be generated.
Watchdog reset mode: both the watchdog interrupt and watchdog reset are enabled.
When this mode is selected, the watchdog counter reaching the value specified by WDWARNINT
will set the WDINT flag and the Watchdog interrupt request will be generated. The watchdog
counter reaching zero will reset the microcontroller.
Other causes for a watchdog reset are: A watchdog feed or changing the WDTC value (if the
WDPROTECT bit is set in the MOD register) before reaching the value of WDWINDOW.
Bit
23:0
31:24
Bit
7:0
31:8
Symbol
WDTC
-
Symbol
Feed
-
All information provided in this document is subject to legal disclaimers.
Description
Watchdog time-out interval.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Description
Feed value should be 0xAA followed by 0x55.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Rev. 1.1 — 10 March 2011
Chapter 17: LPC122x Windowed Watchdog Timer (WWDT)
WDCLK
× 256 × 4.
UM10441
© NXP B.V. 2011. All rights reserved.
Reset value
-
-
Reset value
0x00 FFFF
-
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