OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 59

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
6.3.3 Pin drive
6.3.4 Open-drain mode
6.3.5 A/D-mode
6.3.6 I
6.3.7 Programmable glitch filter
Two levels of output drive can be selected for each normal-drive pin, named low mode
and high mode. Four pins (PIO0_27, PIO0_28, PIO0_29, PIO0_12) are designated
high-drive pins with a high mode and low mode output drive. For details see the LPC122x
data sheet.
An open-drain mode can be enabled for all digital I/O pins. Unless for pins PIO0_10 and
PIO0_11, this mode is not a true open-drain mode. The input cannot be pulled up above
V
In A/D-mode, the digital receiver is disconnected to obtain an accurate input voltage for
analog-to-digital conversions. This mode is available in those IOCON registers that
control pins which can function as ADC inputs. If A/D mode is selected, the pin mode
setting has no effect.
The I
mode independently of whether the I2C function is selected or another digital function. If
the I
Fast-mode plus, are supported. A digital glitch filter can be configured for all functions.
Pins PIO0_10 and PIO0_11 operate as high-current sink drivers (20 mA) independently of
the programmed function.
All PIO pins are equipped with a programmable, digital glitch filter. The filter rejects input
pulses with a selectable duration of shorter than one, two, or three cycles of a filter clock
(S_MODE = 1, 2, or 3). The filter clock can be selected from one of seven peripheral
clocks PCLK0 to 6, which are derived from the main clock (see
IOCONFIGCLKDIV0 to 6 (see
entirely.
Any input pulses of duration T
T
Input pulses of one filter clock cycle longer may also be rejected:
T
Remark: The filtering effect is accomplished by requiring that the input signal be stable for
(S_MODE +1) successive edges of the filter clock before being passed on to the chip.
Enabling the filter results in delaying the signal to the internal logic and should be done
only if specifically required by an application. For high-speed or time critical functions, for
example the timer capture inputs or the SSP function, ensure that the filter is bypassed.
If the delay of the input signal must be minimized, select a faster PCLK and a higher
sample mode (S_MODE) to minimize the effect of the potential extra clock cycle.
2
pulse
pulse
DD(IO)
C-bus mode
2
2
C function is selected, all three I
C-bus pins PIO0_10 and PIO0_11 can be programmed to support a true open-drain
< T
= T
.
PCLKn
PCLKn
× S_MODE
All information provided in this document is subject to legal disclaimers.
× (S_MODE + 1)
Rev. 1.1 — 10 March 2011
pulse
Table
of either polarity will be rejected if:
Chapter 6: LPC122x I/O configuration (IOCONFIG)
31) registers. The filter can also be bypassed
2
C modes, Standard mode, Fast-mode, and
Figure
UM10441
3) using the
© NXP B.V. 2011. All rights reserved.
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