OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 307

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
20.6 Code Read Protection (CRP)
UM10441
User manual
20.5.5.4 ISP flow control
20.5.5.5 ISP command abort
20.5.5.6 Interrupts during ISP
20.5.5.7 Interrupts during IAP
20.5.5.8 RAM used by ISP command handler
20.5.5.9 RAM used by IAP command handler
A software XON/XOFF flow control scheme is used to prevent data loss due to buffer
overrun. When the data arrives rapidly, the ASCII control character DC3 (stop) is sent to
stop the flow of data. Data flow is resumed by sending the ASCII control character DC1
(start). The host should also support the same flow control scheme.
Commands can be aborted by sending the ASCII control character "ESC". This feature is
not documented as a command in
ISP command handler waits for a new command.
The boot block interrupt vectors located in the boot block of the flash are active after any
reset.
The on-chip flash memory is not accessible during erase/write operations. When the user
application code starts executing the interrupt vectors from the user flash area are active.
The user should either disable interrupts, or ensure that user interrupt vectors are active in
RAM and that the interrupt handlers reside in RAM, before making a flash erase/write IAP
call. The IAP code does not use or disable interrupts.
ISP commands use on-chip RAM from 0x1000 017C to 0x1000 025B. The user could use
this area, but the contents may be lost upon reset. Flash programming commands use the
top 32 bytes of on-chip RAM. The stack is located at RAM top − 32. The maximum stack
usage is 256 bytes and it grows downwards.
Flash programming commands use the top 32 bytes of on-chip RAM. The maximum stack
usage in the user allocated stack space is 128 bytes and it grows downwards.
Code Read Protection is a mechanism that allows the user to enable different levels of
security in the system so that access to the on-chip flash and use of the ISP can be
restricted. When needed, CRP is invoked by programming a specific pattern in flash
location at 0x0000 02FC. IAP commands are not affected by the code read protection.
Important: any CRP change becomes effective only after the device has gone
through a power cycle.
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 March 2011
Section
20.7. Once the escape code is received the
Chapter 20: LPC122x Flash ISP/IAP
UM10441
© NXP B.V. 2011. All rights reserved.
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