OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 251

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
13.7.13 Rules for single edge controlled PWM outputs
Table 232. PWM Control Register (PWMC, address 0x4001 0074 and 0x4001 4074 (CT16B1))
Note: When the match outputs are selected to perform as PWM outputs, the timer reset
(MRnR) and timer stop (MRnS) bits in the Match Control Register MCR must be set to
zero except for the match register setting the PWM cycle length. For this register, set the
MRnR bit to one to enable the timer reset when the timer value matches the value of the
corresponding match register.
Bit
1
2
3
31:4
1. All single edge controlled PWM outputs go LOW at the beginning of each PWM cycle
2. Each PWM output will go HIGH when its match value is reached. If no match occurs
3. If a match value larger than the PWM cycle length is written to the match register, and
4. If a match register contains the same value as the timer reset value (the PWM cycle
5. If a match register is set to zero, then the PWM output will go to HIGH the first time the
(timer is set to zero) unless their match value is equal to zero.
(i.e. the match value is greater than the PWM cycle length), the PWM output remains
continuously LOW.
the PWM signal is HIGH already, then the PWM signal will be cleared on the next start
of the next PWM cycle.
length), then the PWM output will be reset to LOW on the next clock tick. Therefore,
the PWM output will always consist of a one clock tick wide positive pulse with a
period determined by the PWM cycle length (i.e. the timer reload value).
timer goes back to zero and will stay HIGH continuously.
Symbol
PWMEN1
PWMEN2
PWMEN3
-
bit description
All information provided in this document is subject to legal disclaimers.
Value
0
1
0
1
0
1
Rev. 1.1 — 10 March 2011
Chapter 13: LPC122x 16-bit Counter/timer 0/1 (CT16B0/1)
Description
PWM mode enable for channel1.
CT16Bi_MAT01 is controlled by EM1.
PWM mode is enabled for CT16Bi_MAT1.
PWM mode enable for channel2.
CT16Bi_MAT2 is controlled by EM2.
PWM mode is enabled for CT16Bi_MAT2.
PWM mode enable for channel3.
CT16Bi_MAT3 is controlled by EM3.
PWM mode is enabled for CT16Bi_MAT3.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is
not defined.
UM10441
© NXP B.V. 2011. All rights reserved.
Reset
value
0
0
0
NA
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