OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 430

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
Table 262. RTC interrupt clear register (ICR - address
Table 263. Register overview: Watchdog timer (base
Table 264. Watchdog Mode register (MOD - 0x4000 4000)
Table 265. Watchdog operating modes selection . . . . . .283
Table 266. Watchdog Timer Constant register (TC - 0x4000
Table 267. Watchdog Feed register (FEED - 0x4000 4008)
Table 268. Watchdog Timer Value register (TV - 0x4000
Table 269: Watchdog Timer Clock Source Selection register
Table 270. Watchdog Timer Warning Interrupt register
Table 271. Watchdog Timer Window register (WINDOW -
Table 272. Comparator pin description . . . . . . . . . . . . . .289
Table 273. Register overview: Comparator (base address
Table 274. Comparator control register (CMP, address
Table 275. Voltage ladder register (VLAD, address 0x4005
Table 276. ADC pin description . . . . . . . . . . . . . . . . . . . .295
Table 277. Register overview: ADC (base address 0x4002
Table 278. A/D Control Register (CR - address
Table 279. A/D Global Data Register (GDR - address
Table 280. A/D Interrupt Enable Register (INTEN - address
Table 281. A/D Data Registers (DR0 to DR7 - addresses
Table 282. A/D Status Register (STAT - address
Table 283. A/D Trim register (TRM - address 0x4002 4034)
Table 284. LPC122x flash configurations . . . . . . . . . . . .301
Table 285. Flash configuration of the LPC122x. . . . . . . .303
Table 286. Code Read Protection options . . . . . . . . . . . .308
Table 287. Code Read Protection hardware/software
Table 288. ISP commands allowed for different CRP
Table 289. ISP command summary. . . . . . . . . . . . . . . . .310
Table 290. ISP Unlock command . . . . . . . . . . . . . . . . . .310
Table 291. ISP Set Baud Rate command . . . . . . . . . . . . 311
Table 292. ISP Echo command . . . . . . . . . . . . . . . . . . . . 311
Table 293. ISP Write to RAM command . . . . . . . . . . . . .312
Table 294. ISP Read Memory command. . . . . . . . . . . . .312
Table 295. ISP Prepare sector(s) for write operation
Table 296. ISP Copy command . . . . . . . . . . . . . . . . . . . .313
UM10441
User manual
0x4005 001C) bit description . . . . . . . . . . . . .277
address 0x4000 4000) . . . . . . . . . . . . . . . . . .280
bit description . . . . . . . . . . . . . . . . . . . . . . . .281
4004) bit description . . . . . . . . . . . . . . . . . . . .283
bit description . . . . . . . . . . . . . . . . . . . . . . . . .283
400C) bit description. . . . . . . . . . . . . . . . . . . .284
(CLKSEL - address 0x4000 4010) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .284
(WARNINT - 0x4000 4014) bit description . . .285
0x4000 4018) bit description . . . . . . . . . . . . .285
0x4005 4000) . . . . . . . . . . . . . . . . . . . . . . . . .289
0x4005 4000) bit description
4004) bit description . . . . . . . . . . . . . . . . . . . .291
0000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296
0x4002 0000) bit description . . . . . . . . . . . . .297
0x4002 0004) bit description . . . . . . . . . . . . .298
0x4002 000C) bit description . . . . . . . . . . . . .298
0x4002 0010 to 0x4002 002C) bit description 299
0x4002 0030) bit description . . . . . . . . . . . . .299
bit description . . . . . . . . . . . . . . . . . . . . . . . . .299
interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . .308
levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309
command . . . . . . . . . . . . . . . . . . . . . . . . . . . .313
. . . . . . . . . . . .289
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 March 2011
Table 297. ISP Go command . . . . . . . . . . . . . . . . . . . . . 314
Table 298. ISP Erase sector command . . . . . . . . . . . . . 314
Table 299. ISP Blank check sector command . . . . . . . . 315
Table 300. ISP Read Part Identification command . . . . . 315
Table 301. LPC122x part identification numbers . . . . . . 315
Table 302. ISP Read Boot Code version number
Table 303. ISP Compare command . . . . . . . . . . . . . . . . 316
Table 304. ReadUID command. . . . . . . . . . . . . . . . . . . . 316
Table 305. ISP Return Codes Summary. . . . . . . . . . . . . 317
Table 306. IAP Command Summary . . . . . . . . . . . . . . . 319
Table 307. IAP Prepare sector(s) for write operation
Table 308. IAP Copy RAM to flash command. . . . . . . . . 320
Table 309. IAP Erase Sector(s) command . . . . . . . . . . . 321
Table 310. IAP Blank check sector(s) command . . . . . . 321
Table 311. IAP Read Part Identification command . . . . . 321
Table 312. IAP Read Boot Code version number
Table 313. IAP Compare command . . . . . . . . . . . . . . . . 322
Table 314. IAP Reinvoke ISP . . . . . . . . . . . . . . . . . . . . . 322
Table 315. IAP ReadUID command . . . . . . . . . . . . . . . . 323
Table 316. IAP Erase page command . . . . . . . . . . . . . . 323
Table 317. IAP Erase info page command . . . . . . . . . . . 323
Table 318. IAP Status Codes Summary . . . . . . . . . . . . . 324
Table 319. DMA connections . . . . . . . . . . . . . . . . . . . . . 327
Table 320. Register overview: micro DMA (base address
Table 321. DMA status register (DMA_STATUS, address
Table 322. DMA configuration register (DMA_CFG, address
Table 323. Channel control base pointer register
Table 324. Channel alternate control base pointer register
Table 325. Channel wait on request status register
Table 326. Channel software request register
Table 327. Channel useburst set register
Table 328. Channel useburst clear register
Table 329. Channel request mask set register
Table 330. Channel request mask clear register
Table 331. Channel enable set register
command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
0x4004 C000)
0x4004 C000) bit description . . . . . . . . . . . . . 329
0x4004 C004) bit description . . . . . . . . . . . . . 329
(CTRL_BASE_PTR, address 0x4004 C008) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
(ATL_CTRL_BASE_PTR, address 0x4004 C00C)
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 330
(DMA_WAITONREQ_STATUS, address 0x4004
C010) bit description . . . . . . . . . . . . . . . . . . . 330
(CHNL_SW_REQUEST, address 0x4004 C014)
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 331
(CHNL_USEBURST_SET, address 0x4004
C018) bit description . . . . . . . . . . . . . . . . . . . 331
(CHNL_USEBURST_CLR, address 0x4004
C01C) bit description . . . . . . . . . . . . . . . . . . . 332
(CHNL_REQ_MASK_SET, address 0x4004
C020) bit description . . . . . . . . . . . . . . . . . . . 332
(CHNL_REQ_MASK_CLR, address 0x4004
C024) bit description . . . . . . . . . . . . . . . . . . . 333
(CHNL_ENABLE_SET, address 0x4004 C028) bit
Chapter 26: Supplementary information
. . . . . . . . . . . . . . . . . . . . . . . 328
UM10441
© NXP B.V. 2011. All rights reserved.
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