OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 200

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
11.10.1 Master Transmitter mode
In the master transmitter mode, a number of data bytes are transmitted to a slave receiver
(see
initialized as follows:
Table 197. CONSET used to initialize Master Transmitter mode
The I
to logic 1 to enable the I
its own slave address or the General Call address in the event of another device
becoming master of the bus. In other words, if AA is reset, the I
slave mode. STA, STO, and SI must be reset.
The master transmitter mode may now be entered by setting the STA bit. The I
now test the I
When a START condition is transmitted, the serial interrupt flag (SI) is set, and the status
code in the status register (STAT) will be 0x08. This status code is used by the interrupt
service routine to enter the appropriate state service routine that loads DAT with the slave
address and the data direction bit (SLA+W). The SI bit in CON must then be reset before
the serial transfer can continue.
When the slave address and the direction bit have been transmitted and an
acknowledgment bit has been received, the serial interrupt flag (SI) is set again, and a
number of status codes in STAT are possible. There are 0x18, 0x20, or 0x38 for the
master mode and also 0x68, 0x78, or 0xB0 if the slave mode was enabled (AA = logic 1).
The appropriate action to be taken for each of these status codes is detailed in
After a repeated START condition (state 0x10). The I
receiver mode by loading DAT with SLA+R).
Bit
Symbol
Value
Figure
2
C rate must also be configured in the SCLL and SCLH registers. I2EN must be set
7
-
-
22). Before the master transmitter mode can be entered, CON must be
2
C-bus and generate a START condition as soon as the bus becomes free.
All information provided in this document is subject to legal disclaimers.
6
I2EN
1
Rev. 1.1 — 10 March 2011
2
C block. If the AA bit is reset, the I
5
STA
0
4
STO
0
Chapter 11: LPC122x I2C-bus controller
3
SI
0
2
C block may switch to the master
2
C block will not acknowledge
2
AA
x
2
C interface cannot enter a
UM10441
-
-
1
© NXP B.V. 2011. All rights reserved.
2
C logic will
Table
0
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200 of 442
199.