OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 333

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
21.6.12 Channel enable clear register
21.6.11 Channel enable set register
Table 330. Channel request mask clear register (CHNL_REQ_MASK_CLR, address 0x4004
This register is a read/write register and enables a DMA channel c (c = 0 to 20). Reading
the register returns the enable status of the channels. Writing to a bit where a DMA
channel is not implemented has no effect.
Table 331. Channel enable set register (CHNL_ENABLE_SET, address 0x4004 C028) bit
This register is a write-only register and disables a DMA channel. Writing to a bit where a
DMA channel is not implemented has no effect.
Remark: The controller disables a channel by setting the appropriate bit when either:
Bit
20:0
31:21 -
Bit
20:0
31:21 -
•
•
•
The controller completes the DMA cycle.
The controller reads a channel_cfg memory location which has cycle_ctrl = 000.
An error occurs on the AHB-Lite bus.
Symbol
CHNL_ENABLE_
SET
Symbol
CHNL_REQ_
MASK_CLR
C024) bit description
description
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 March 2011
Chapter 21: LPC122x General purpose micro DMA controller
Description
Set the appropriate bit to enable DMA requests for the channel
corresponding to dma_req[c] and dma_sreq[c].
Write as:
Bit [c] = 0: No effect. Use the chnl_req_mask_set Register to
disable dma_req[c] and dma_sreq[c] from generating requests.
Bit [c] = 1: Enables dma_req[c] or dma_sreq[c] to generate
DMA requests.
Reserved.
Description
Returns the enable status of the channels, or enables the
corresponding channels.
Read as:
Bit [c] = 0: Channel c is disabled.
Bit [c] = 1 Channel c is enabled.
Write as:
Bit [c] = 0: No effect. Use the CHNL_ENABLE_CLR Register
to disable a channel.
Bit [c] = 1: Enables channel c.
Reserved.
UM10441
© NXP B.V. 2011. All rights reserved.
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Reset
value
0x0
-
Reset
value
-
-