OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 226

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
12.6.2 SSP Control Register 1
Table 206. SSP Control Register 0 (CR0 - address 0x4004 0000) bit description
This register controls certain aspects of the operation of the SSP controller.
Table 207. SSP Control Register 1 (CR1 - address 0x4004 0004) bit description
Bit
6
7
15:8
31:16 -
Bit
0
1
2
3
31:4
Symbol Value
CPOL
CPHA
SCR
Symbol
LBM
SSE
MS
SOD
-
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0
1
0
1
Value
0
1
0
1
0
1
Rev. 1.1 — 10 March 2011
Description
Clock Out Polarity. This bit is only used in SPI mode.
SSP controller maintains the bus clock low between frames.
SSP controller maintains the bus clock high between frames.
Clock Out Phase. This bit is only used in SPI mode.
SSP controller captures serial data on the first clock transition
of the frame, that is, the transition away from the inter-frame
state of the clock line.
SSP controller captures serial data on the second clock
transition of the frame, that is, the transition back to the
inter-frame state of the clock line.
Serial Clock Rate. The number of prescaler-output clocks per
bit on the bus, minus one. Given that CPSDVSR is the
prescale divider, and the APB clock PCLK clocks the
prescaler, the bit frequency is PCLK / (CPSDVSR × [SCR+1]).
Reserved.
Description
Loop Back Mode.
During normal operation.
Serial input is taken from the serial output (MOSI or MISO)
rather than the serial input pin (MISO or MOSI
respectively).
SSP Enable.
The SSP controller is disabled.
The SSP controller will interact with other devices on the
serial bus. Software should write the appropriate control
information to the other SSP registers and interrupt
controller registers, before setting this bit.
Master/Slave Mode.This bit can only be written when the
SSE bit is 0.
The SSP controller acts as a master on the bus, driving the
SCLK, MOSI, and SSEL lines and receiving the MISO line.
The SSP controller acts as a slave on the bus, driving
MISO line and receiving SCLK, MOSI, and SSEL lines.
Slave Output Disable. This bit is relevant only in slave
mode (MS = 1). If it is 1, this blocks this SSP controller
from driving the transmit data line (MISO).
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Chapter 12: LPC122x SSP controller
UM10441
© NXP B.V. 2011. All rights reserved.
Reset
value
0
0
0
0
NA
226 of 442
Reset
value
0
0
0x00
-