OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 372

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
25.3.3.6.1 Exception entry
25.3.3.6 Exception entry and return
Assigning a higher priority value to IRQ[0] and a lower priority value to IRQ[1] means that
IRQ[1] has higher priority than IRQ[0]. If both IRQ[1] and IRQ[0] are asserted, IRQ[1] is
processed before IRQ[0].
If multiple pending exceptions have the same priority, the pending exception with the
lowest exception number takes precedence. For example, if both IRQ[0] and IRQ[1] are
pending and have the same priority, then IRQ[0] is processed before IRQ[1].
When the processor is executing an exception handler, the exception handler is
preempted if a higher priority exception occurs. If an exception occurs with the same
priority as the exception being handled, the handler is not preempted, irrespective of the
exception number. However, the status of the new interrupt changes to pending.
Descriptions of exception handling use the following terms:
Preemption — When the processor is executing an exception handler, an exception can
preempt the exception handler if its priority is higher than the priority of the exception
being handled.
When one exception preempts another, the exceptions are called nested exceptions. See
Section 25–25.3.3.6.1
Return — This occurs when the exception handler is completed, and:
The processor pops the stack and restores the processor state to the state it had before
the interrupt occurred. See
Tail-chaining — This mechanism speeds up exception servicing. On completion of an
exception handler, if there is a pending exception that meets the requirements for
exception entry, the stack pop is skipped and control transfers to the new exception
handler.
Late-arriving — This mechanism speeds up preemption. If a higher priority exception
occurs during state saving for a previous exception, the processor switches to handle the
higher priority exception and initiates the vector fetch for that exception. State saving is
not affected by late arrival because the state saved would be the same for both
exceptions. On return from the exception handler of the late-arriving exception, the normal
tail-chaining rules apply.
Exception entry occurs when there is a pending exception with sufficient priority and
either:
When one exception preempts another, the exceptions are nested.
•
•
•
•
there is no pending exception with sufficient priority to be serviced
the completed exception handler was not handling a late-arriving exception.
the processor is in Thread mode
the new exception is of higher priority than the exception being handled, in which case
the new exception preempts the exception being handled.
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 March 2011
for more information.
Section 25–25.3.3.6.2
Chapter 25: LPC122x Appendix ARM Cortex-M0
for more information.
UM10441
© NXP B.V. 2011. All rights reserved.
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