OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 271

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
15.5 Register description
Table 249. Register overview: SysTick timer (base address 0xE000 E000)
[1]
UM10441
User manual
Name
SYST_CSR
SYST_RVR
SYST_CVR
SYST_CALIB
Reset Value reflects the data stored in used bits only. It does not include content of reserved bits.
15.5.1 System Timer Control and status register
Access
R/W
R/W
R/W
R/W
Since the SysTick timer is a part of the Cortex-M0, it facilitates porting of software by
providing a standard timer that is available on Cortex-M0 based devices. The SysTick
timer can be used for:
Refer to the Cortex-M0 User Guide for details.
The systick timer registers are located on the ARM Cortex-M0 private peripheral bus (see
Figure
Section
The SYST_CSR register contains control information for the SysTick timer and provides a
status flag. This register is part of the ARM Cortex-M0 core system timer register block.
For a bit description of this register, see
This register determines the clock source for the system tick timer.
Table 250. SysTick Timer Control and status register (SYST_CSR - 0xE000 E010) bit
Bit
0
1
2
•
•
•
•
An RTOS tick timer which fires at a programmable rate (for example 100 Hz) and
invokes a SysTick routine.
A high-speed alarm timer using the core clock.
A simple counter. Software can use this to measure time to completion and time used.
An internal clock source control based on missing/meeting durations. The
COUNTFLAG bit-field in the control and status register can be used to determine if an
action completed within a set duration, as part of a dynamic clock management
control loop.
Address
offset
0x010
0x014
0x018
0x01C
63), and are part of the ARM Cortex-M0 core peripherals. For details, see
Symbol
ENABLE
TICKINT
CLKSOURCE Reserved
25.5.4.
description
All information provided in this document is subject to legal disclaimers.
Description
System Tick counter enable. When 1, the counter is enabled.
When 0, the counter is disabled.
System Tick interrupt enable. When 1, the System Tick interrupt
is enabled. When 0, the System Tick interrupt is disabled. When
enabled, the interrupt is generated when the System Tick counter
counts down to 0.
System Timer Reload value register
Description
System Timer Control and status register
System Timer Current value register
System Timer Calibration value register
Rev. 1.1 — 10 March 2011
Chapter 15: LPC122x System Tick (SysTick) timer
Section
25.5.4.
UM10441
Reset value
0x000 0000
0
0
0x1F
© NXP B.V. 2011. All rights reserved.
271 of 442
Reset
value
0
0
0
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