OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 189

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
11.7.7.2 Loss of arbitration in Monitor mode
11.7.8 I
11.7.9 I
Following all of these interrupts, the processor may read the data register to see what was
actually transmitted on the bus.
In monitor mode, the I
the bus master or issue an ACK). Some other slave on the bus will respond instead. This
will most probably result in a lost-arbitration state as far as our module is concerned.
Software should be aware of the fact that the module is in monitor mode and should not
respond to any loss of arbitration state that is detected. In addition, hardware may be
designed into the module to block some/all loss of arbitration states from occurring if those
state would either prevent a desired interrupt from occurring or cause an unwanted
interrupt to occur. Whether any such hardware will be added is still to be determined.
These registers are readable and writable and are only used when an I
to slave mode. In master mode, this register has no effect. The LSB of I2ADR is the
General Call bit. When this bit is set, the General Call address (0x00) is recognized.
Any of these registers which contain the bit 00x will be disabled and will not match any
address on the bus. All four registers (including the I2ADR0 register) will be cleared to this
disabled state on reset.
Table 191. I
In monitor mode, the I
the ENA_SCL bit is not set. This means that the processor will have a limited amount of
time to read the contents of the data received on the bus. If the processor reads the I2DAT
shift register, as it ordinarily would, it could have only one bit-time to respond to the
interrupt before the received data is overwritten by new data.
To give the processor more time to respond, a new 8-bit, read-only DATA_BUFFER
register will be added. The contents of the 8 MSBs of the I2DAT shift register will be
transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus
ACK or NACK) has been received on the bus. This means that the processor will have
nine bit transmission times to respond to the interrupt and read the data before it is
overwritten.
The processor will still have the ability to read I2DAT directly, as usual, and the behavior of
I2DAT will not be altered in any way.
Although the DATA_BUFFER register is primarily intended for use in monitor mode with
the ENA_SCL bit = ‘0’, it will be available for reading at any time under any mode of
operation.
Bit Symbol
0
7:1 Address
31:
8
2
2
C Slave Address registers (ADR[1, 2, 3]- 0x4000 00[20, 24, 28])
C Data buffer register (DATA_BUFFER - 0x4000 002C)
GC
-
0x4000 0028) bit description
2
C Slave Address registers (ADR1 - 0x4000 0020, ADR2 - 0x4000 0024, ADR3 -
All information provided in this document is subject to legal disclaimers.
Description
General Call enable bit.
The I
Reserved
2
C device address for slave mode.
2
2
Rev. 1.1 — 10 March 2011
C module will not be able to respond to a request for information by
C module may lose the ability to stretch the clock (stall the bus) if
Chapter 11: LPC122x I2C-bus controller
UM10441
2
© NXP B.V. 2011. All rights reserved.
C interface is set
0x00
Reset value
0
-
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