OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 180

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

11.1 How to read this chapter
11.2 Basic configuration
11.3 Features
11.4 Applications
11.5 Description
UM10441
User manual
The I
The peripheral clock to the I2C block I2C_PCLK is provided by the system clock, which is
controlled by the SYSAHBCLKDIV register
through the System AHB clock control register bit 5
Interfaces to external I
other microcontrollers, etc.
A typical I
direction bit (R/W), two types of data transfers are possible on the I
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UM10441
Chapter 11: LPC122x I2C-bus controller
Rev. 1.1 — 10 March 2011
Standard I
Master/Slave.
Arbitration is handled between simultaneously transmitting masters without corruption
of serial data on the bus.
Programmable clock allows adjustment of I
Data transfer is bidirectional between masters and slaves.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization is used as a handshake mechanism to suspend and
resume serial transfer.
Supports Fast-mode Plus.
Optional recognition of up to four distinct slave addresses.
Monitor mode allows observing all I
I
The I
Data transfer from a master transmitter to a slave receiver. The first byte transmitted
by the master is the slave address. Next follows a number of data bytes. The slave
returns an acknowledge bit after each received byte.
2
2
C-bus can be used for test and diagnostic purposes.
C-bus controller is available on all LPC122x parts.
2
2
C block contains a standard I
C-bus configuration is shown in
2
C-compliant bus interfaces may be configured as Master, Slave, or
All information provided in this document is subject to legal disclaimers.
2
Rev. 1.1 — 10 March 2011
C standard parts, such as serial RAMs, LCDs, tone generators,
2
2
C-compliant bus interface with two pins.
C-bus traffic, regardless of slave address.
Figure
(Table
2
C transfer rates.
13. Depending on the state of the
21). The I2C block can be disabled
(Table
21) for power savings.
2
C-bus:
© NXP B.V. 2011. All rights reserved.
User manual
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